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1、Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIALEffio-P / Effio-S System Programmers ManualVer.1.0Effio-Pand Effio-S is a trademark of Sony corporation.Sony Corporation1Technical Information - Effio-P / Effio-S System Programmers Manu

2、al -Tentative ver.1.0 October 4, 2010CONFIDENTIALUpdate Record:1Version numberDateContents of revisionNote1.02010/10/4Fitst Edition-Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIALNotes:The contents of this document are subject to cha

3、nge without notice due to improvements. Sony does not intend for this document to constitute a license to implement the industrial property rights relating to its contents or constitute guarantees for any other rights.When circuit examples are provided in the document, they indicate typical applicat

4、ions examples as a reference regarding their usage: therefore, Sony will not be liable in any way for damages resulting from the use of these circuits.It is forbidden to copy, transfer or transmit the contents of this document without the written authorization ofSony Corporation.2Technical Informati

5、on - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIALIndex:1.Boot81.1.Overview of functions.1.4.External pin interfacesFlow during internal Flash boot ROM boot flow89101.5.External Flash boot1111.5.2.Overview of external Flash bootExternal F

6、lash boot procedure2.Clock, Reset（Clock, Reset）.2.3.Overview of functionsClock frequencies of the blocks Reset control1414143.Memory map.OverviewMemory map15153.3.Remap163.4.Restrictions164.Pin settings174.1.Overview of functions.4.4.Common pin function selection Pull-up/p

7、ull-down controlPin drive capacity switching1718214.5.Precautions and restrictions225.ARM946E-S（built-in user microcontroller）235.1.Overview of functions.5.4.External pin interfaces232424Clock settingReset setting5.5.Interrupts.Memory mapRestrictions2425255.7.1.Semaphore instructio

8、ns3Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIAL5.7.2.Concerning the memory protection unit (MPU) settings256.Interrupt Controller (INTC)2.6.3.Overview of functionsExternal pin interfaces Clock setting26262.6.6.Rese

9、t setting InterruptsDescription of operation26272929293..3.Assignment of interrupt sources to IRQ exceptions and FIQ exceptions IRQ exception operationsFIQ exception operations7.External Interrupt Controller (EXTINT)3.7.3.Overview of functions External pin interfacesClock sett

10、ing37373.Reset settingInterrupts3738383939404040404..3.EXBUSYSG_TGVD_N SG_ FLD7.6.Description of operation..3.MailboxPrecautions concerning interrupt processingPrecautions concerning level detection interrupts Precautions concerning edge detection interrupts8.8.1

11、..Clock settingExternal pin interfaces Reset setting41414.8.6.Interrupts414242434649Communication protocolCommunication procedure.6.2.Processing by interrupt factor pollingProcessing by IRQ interrupt8.7.Precautions and restrictions9.TIMER（TIMER ch0 to ch3）50.Overview of

12、functionsExternal pin interfaces50504Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIAL9.3.Clock setting509.4.Reset setting50.9.7.InterruptsDescription of operation Startup procedure5052529.8.Precautions and restrictions5310.Watc

13、hdog Timer (WDT)5410.1.Overview of functions54.10.4.External pin interfaces Clock settingReset setting54545454555656575710.4.1.Reset output.InterruptsDescription of operation0.6.2.Basic operationsWatchdog Timer operation method10.7.Precautions and restrictions11.PWM (PWM ch

14、0 to ch3)58.11.3.Overview of functionsExternal pin interfaces Clock setting58585811.4.Reset setting58.InterruptsDescription of operation595959606161.6.3.I2C (I2C)Overview of operation Operation methodPrecautions for use12.12.1.Overview of functions6.12.4.E

15、xternal pin interfacesClock setting626263Reset setting.12.7.InterruptsBit transfer rate calculation ICDS and ICDH register settings63646612.8.Access to buffer RAM used for transfer data675Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010C

16、ONFIDENTIAL12.9.Function for suppressing noise on I2C bus6712.10.Transfer format682.Outline of initialization processingMaster transfer70717176818712.12.1. Automatic transfer in master mode12.12.2. Normal data transfer in master mode4.Slave mode transferTransfer of data with bit

17、lengths other than 8 bits6.Free data format transferPrecautions and restrictions888913.Universal Asynchronous Receiver Transmitter (UART0/UART1)9013.1.Overview of functions90.13.4.External pin interfaces Clock settingReset setting90909013.5.Interrupts9191919393939596969697979813.5

18、..Overrunning error interruptBreak error interrupt13.6.Description of operation3.6.8.SYSREG setting Baud rate generation Character frameTransmitting and receiving data Disabling FIFOError bitsHardware flow control System/diagnosis loopback te

19、st13.7.Transmission sequence13.8.Receive sequence9913.9.Precautions and restrictions10014.Serial Peripheral Interface（SPI）10114.1.Overview of functions10.14.4.External pin interfaces Clock settingReset setting10110310314.5.Interrupts1041041054.5.2.Transmit FIFO interruptReceive FIF

20、O interrupt6Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIAL4.5.4.Receive time-out interruptReceive overrun interrupt10510510510510510710710711011411514.6.Description of operation4.6.3.SYSREG settings Control re

21、gister settingsSetting of transmission and receive data14.7.Frame formats4.7.3.Texas Instruments synchronous serial frame format Motorola SPI frame formatNational Semiconductor Microwire frame format14.8.Precautions and restrictions15.GPIO (GPIO ch0, ch1)116.15.3.Function ove

22、rviewExternal pin interface Clock setting116116118.15.6.Reset setting InterruptsGPIO data read/write11811811815.7.Multiple-use function11816.A/D Converter (ADC)119.Overview of functionsExternal pin interfaces119119.16.5.Clock setting Reset settingInterrupts11911912016.6.De

23、scription of operation121121122126.6.3.Single-channel conversionMultiple-channel conversion Low power consumption mode17.Built-in user microcontroller1237Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIAL1.Boot1.1. Overv

24、iew of functionsThere are three ways to boot the CXD4129/4130. Internal Flash bootExternal Flash boot Internal ROM bootAs a basic rule, the CXD4129/4130 is booted from the internal Flash, and the system then operates. External Flash boot and internal ROM boot are used as a rule when writing data int

25、o the Flash incorporated inside the CXD4129/4130.Furthermore, booting from the internal Flash as described in this manual applies in cases where the internal user microcontroller is used. The operations in this manual have no relevance when an externalmicrocontroller is used.1.2. External pin interf

26、acesThe CXD4129/4130 is normally booted from the internal Flash. Booting from the external flash memory or internal ROM is accomplished by connecting the external pins shown in Table 1-1 External pins and Fig. 1-1to pull-up resistors.Table 1-1 External pins(*1) These pins serve as input pins when CX

27、D4129/4130 system reset is at the “L” level.The boot mode is determined by the pin status when system reset is “L.”Fig. 1-1 Pin connection diagram8Pin No.SymbolI/ODescriptionB5DO6O(*1)ROM/internal flash memory boot selection pinA4DO7O(*1)External flash memory/internal flash memory boot selection pin

28、Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIAL1.3. Flow during internal Flash bootIn the internal Flash boot mode, the CXD4129/4130 is booted from the Flash incorporated internally.In the CXD4129/4130, first the system reset is rele

29、ased, and then the internal microcontroller starts up. After startup, the mode settings are established, and then the internal user microcontroller starts up. The internal user microcontroller will not start up unless the following conditions are met. When the “Use the internal user microcontroller”

30、 setting is established in the internal Flash parameter area When the “Use the internal user microcontroller” setting is established even though the “Do not use the internal user microcontroller” setting is established in the internal Flash parameter area or the data in theparameter area is invalid

31、dataFig.1-2 shows the processing flow during internal flash memory boot.Fig. 1-2 Processing flow during internal flash memory bootAfter the internal user microcontroller has started up, it executes commands from the internal flash memory. A 32 kB internal RAM is incorporated so place the stack/heap

32、area and data to be accessed at high speed in the internal RAM area.9Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIAL1.4. ROM boot flowIn the ROM boot mode, the programs and the data for writing the data from UART2 into the internal f

33、lash memory are copied into the internal RAM, and the programs are executed.In order for ROM boot to be executed, the operation mode must be selected in accordance with the statuses ofthe DO4, DO2, DO1 and DO0 pins described later. Based on these settings, the baud rate of UART is set in such a way

34、that the UART transmission rate will be 115.2 kbps using the currently supplied clock.Table 1-2 External pins for operation mode selection(*2) These pins serve as input pins when CXD4129/4130 system reset is at the “L” level.The boot mode is determined by the pin status when system reset is “L.” (*3

35、) This can be set only for the CXD4129.Based on the statuses of the pins listed in Table 1-2, it is possible to determine the operation modes as in Table 1-3 and Table 1-4. The selection of the WD mode in Table 1-4 takes effect for the CXD4129 only. With the CXD4130, the system starts up in the norm

36、al mode regardless of the status of the DO0 pin.Furthermore, “PU” in both Table 1-3 and Table 1-4 means “pull-up” for an external pin. “NC” means “no pull-up”for an external pin.Table 1-3 Operation mode truth table (1)10Pin statusOperation modeDO0DO4DO2DO1NCNCNCNCNTSC 760 Normal (1clock Mode)NCNCNCP

37、UPAL 760 Normal (1clock Mode)NCNCPUNCNTSC 960 Norma l(1clock Mode)NCNCPUPUPAL 960 Normal (1clock Mode)NCPUNCNCNTSC 760 Normal (1clock/2clock Mode)NCPUNCPUPAL 760 Normal (1clock/2clock Mode)NCPUPUNCNTSC 960 Normal (1clock/2clock Mode)NCPUPUPUPAL 960 Normal (1clock/2clock Mode)Pin No.SymbolI/ODescript

38、ionC5DO4O(*2)External sync/0PLL selection pinC3DO2O(*2)960H/760H selection pinC2DO1O(*2)NTSC/PAL selection pinD2DO0O(*2)WD/Normal mode selection pin (*3)Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIALTable 1-4 Operation mode truth ta

39、ble (2) Valid for CXD4129 onlyThe processing flow for ROM boot is described below. During ROM boot, the internal microcontroller is set until UART communication is enabled. Once the setting enable status is established, transfer from the personal computer the programs for writing into the internal F

40、lash as well as the program codes and data to bewritten into the Flash to the internal RAM.1.5. External Flash boot1.5.1. Overview of external Flash bootIn the external Flash boot mode, booting is initiated from the Flash connected outside the CXD4129/4130 rather than from the Flash inside the CXD41

41、29/4130.This is the boot mode for starting up the system from the external Flash and writing the program codes and data into the internal Flash. Compared with ROM boot, the data can be transferred at a higher speed, so datais written at a higher speed in the Flash.In order to start up the system in

42、the external Flash boot mode, connect a pull-up resistor externally to the DO7 pin as shown in Fig. 1-1 Pin connection diagramFig. and Table 1-1 External pins of “1.2 External pin interfaces”.It is also necessary to set the same operation mode as with ROM boot so, as indicated in the “1.4 ROM bootfl

43、ow” set the operation mode using the DO4, DO2 DO1 and DO0 pins.1.5.2. External Flash boot procedureThe procedure for the external flash memory boot is described below..Pull up the DO7 external pin. Use the DO4, DO2, DO1 and DO0 pins to set the operation mode. Supply the clock.Start booting fr

44、om the external Flash by releasing reset.From the CKG_018_STAT register of SYSREG, read the operation mode, and establish the settings for each operation mode.Initialize the embedded DRAM.5.11Pin statusOperation modeDO0DO4DO2DO1PUNCNCNCNTSC 760 WD (1clock Mode)PUNCNCPUPAL 760 WD (1clock Mode)PUNCPUN

45、CNTSC 960 WD (1clock Mode)PUNCPUPUPAL 960 WD (1clock Mode)PUPUNCNCNTSC 760 WD (1clock /2clock Mode)PUPUNCPUPAL 760 WD (1clock /2clock Mode)PUPUPUNCNTSC 960 WD (1clock /2clock Mode)PUPUPUPUPAL 960 WD (1clock /2clock Mode)Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative v

46、er.1.0 October 4, 2010CONFIDENTIAL.10.Copy the downloaded codes stored in the external flash memory into the embedded DRAM. Jump to the downloaded codes.Copy the firmware codes into the embedded DRAM.Initialize the serial flash memory controller so that the internal flash memory is enabled.Wr

47、ite the firmware codes, which were copied into the embedded DRAM, into the internal Flash.12Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIALFig. 1-3 External flash memory boot processing flow13Technical Information - Effio-P / Effio-S

48、 System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDENTIAL2. Clock, Reset（Clock, Reset）2.1. Overview of functionsThese functions are for supplying the clock signals to the blocks and for resetting the blocks.2.2. Clock frequencies of the blocksThe built-in microcontroller sets the clo

49、ck frequencies of the blocks in accordance with the operation mode as shown in Table 2-1.The blocks start up with the clock signals in Table 2-1 supplied.The clock signals have the same frequencies whether the normal mode or the WD mode is established.Table 2-1 Clock frequencies (MHz) of the blocks2

50、.3. Reset controlEach block starts with reset released excluding the ADC block. The reset release of the ADC block iscontrolled by SYSREG. Please refer to the ADC block for details.14Horizontal Pixel760H960HTV FormatNTSCPALPAL(1 clock mode)NTSCPALARM946ES52.49999353.20342553.20312554.00000054.000000

51、INTC52.49999353.20342553.20312554.00000054.000000EXTINT52.49999353.20342553.20312554.00000054.000000Mailbox52.49999353.20342553.20312554.00000054.000000TIMER52.49999353.20342553.20312554.00000054.000000WDT52.49999353.20342553.20312554.00000054.000000PWM52.49999353.20342553.20312554.00000054.000000I2

52、C52.49999353.20342553.20312554.00000054.000000UART52.49999353.20342553.20312554.00000054.000000SPI52.49999353.20342553.20312554.00000054.000000GPIO52.49999353.20342553.20312554.00000054.000000ADC1.6406251.6626071.6625981.6875001.687500Technical Information - Effio-P / Effio-S System Programmers Manual -Tentative ver.1.0 October 4, 2010CONFIDE