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1、HY57V283220(L)T(P)/ HY5V22(L)F(P)4 Banks x 1M x 32Bit Synchronous DRAMRevision HistoryThis document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied.Rev.

2、 0.9 / July 2004Revision No.HistoryRemark0.1Defined Preliminary Specification0.21) Modified FBGA Ball Configuration Typo.2) Changed Functional Block Diagram from A10 to A11.3) Changed VDD min from 3.0V to 3.135V.4) Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf.5) Insert tAC2 Value.6) In

3、sdrt tRAS & CLK Value.0.3Defined IDD Spec.0.4Delited Preliminary.0.5Changed IDD Spec.0.6133MHz Speed Added0.7Changed FBGA Package Size from 11x13 to 8x13.0.81) Changed VDD min from 3.135V to 3.0V.2) Changed VIL min from VSSQ-0.3V to -0.3V.0.9Modified of size erra. (Page15)(Equation : 13.00 10 - 13.0

4、0 0.10)HY57V283220(L)T(P)/ HY5V22(L)F(P)4 Banks x 1M x 32Bit Synchronous DRAMDESCRIPTIONThe Hynix HY57V283220(L)T(P) / HY5V22(L)F(P) is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V283220(L)T(P) / HY5V22(L)F(

5、P) is orga- nized as 4banks of 1,048,576x32.HY57V283220(L)T(P) / HY5V22(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

6、high bandwidth. All input and output voltage levels are compatible with LVTTL.Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count

7、 sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.)FEATURESJEDEC standard 3.3V pow

8、er supplyAuto refresh and self refreshAll device pins are compatible with LVTTL interface4096 refresh cycles / 64ms86TSOP-II, 90Ball FBGA with 0.8mm of pin pitchProgrammable Burst Length and Burst TypeAll inputs and outputs referenced to positive edge of system clock- 1, 2, 4, 8 or full page for Seq

9、uential Burst- 1, 2, 4 or 8 for Interleave BurstData mask function by DQM0,1,2 and 3Programmable CAS Latency ; 2, 3 ClocksInternal four banks operationBurst Read Single Write operationORDERING INFORMATIONNote) Hynix supports lead free part for each speed grade with same specification.This document i

10、s a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied.Rev. 0.9 / July 2004Part No.Clock FrequencyOrganizationInterfacePackageHY57V283220(L)T(P)-5HY5V22(L)F(P)-

11、5200MHz4Banks x 1Mbits x32LVTTL86TSOP-II 90Ball FBGAHY57V283220(L)T(P)-55HY5V22(L)F(P)-55183MHzHY57V283220(L)T(P)-6HY5V22(L)F(P)-6166MHzHY57V283220(L)T(P)-7HY5V22(L)F(P)-7143MHzHY57V283220(L)T(P)-HHY5V22(L)F(P)-H133MHzHY57V283220(L)T(P)-8HY5V22(L)F(P)-8125MHzHY57V283220(L)T(P)-PHY5V22(L)F(P)-P100MHz

12、HY57V283220(L)T(P)-SHY5V22(L)F(P)-S100MHzHY57V283220(L)T(P) / HY5V22(L)F(P)PIN CONFIGURATION ( HY57V283220(L)T(P) Series)V DD DQ 0 V DDQ DQ 1DQ 2 V SS Q DQ 3DQ 4 V DDQ DQ 5DQ 6 V SS Q DQ 7 NC V DD D Q M 0/W E/C A S/R A S/C S A1 1BA 0BA 1 A 10/ A PA 0A 1 A2 DQ M 2 V DD NC D Q 1 6 V SS Q D Q 17D Q 1 8

13、 V D D Q D Q 19D Q 2 0 V SS Q D Q 21DQ 2 2 V DDQ DQ 2 3 V DD 186 V SS D Q 15 V S S Q D Q 14D Q 1 3 V D D Q D Q 12D Q 11 V S S Q D Q 10D Q 9 V D D Q D Q 8 NC V SSD Q M 1 NC NC CL K C K E A 9A 8A 7A 6A 5A 4 A3 DQ M 3 V SS NCD Q 3 1 V D D Q D Q 30D Q 2 9 V S S Q D Q 28D Q 2 7 V D D Q D Q 26DQ 2 5 V SSQ

14、 DQ 2 4 V SS2345678910 11 12 13 14 15 16 17 18 19 20 21 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 8 6 pin TS O P I I400m i l x 875m i l22 65 0 . 5 m m pin pitc h236424632562266127602859295830315756323355543435535236375150494838394746404145444243PIN DESCRIPTIONRev. 0.9 / July 20043P

15、INPIN NAMEDESCRIPTIONCLKClockThe system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK.CKEClock EnableControls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refreshCSChip SelectEnables or disable

16、s all inputs except CLK, CKE and DQMBA0, BA1Bank AddressSelects bank to be activated during RAS activity Selects bank to be read/written during CAS activityA0 A11AddressRow Address : RA0 RA11, Column Address : CA0 CA7 Auto-precharge flag : A10 RAS, CAS, WERow Address Strobe, Column Address Strobe, W

17、rite EnableRAS, CAS and WE define the operation Refer function truth table for detailsDQM03Data Input/Output MaskControls output buffers in read mode and masks input data in write modeDQ0 DQ31Data Input/OutputMultiplexed data input / output pinVDD/VSSPower Supply/GroundPower supply for internal circ

18、uits and input buffersVDDQ/VSSQData Output Power/GroundPower supply for output buffersNCNo ConnectionNo connectionHY57V283220(L)T(P) / HY5V22(L)F(P)Ball CONFIGURATION ( HY5V22(L)F(P) Series)123456789ABCDEFGHJKLMNPRBall DESCRIPTIONRev. 0.9 / July 20044PINPIN NAMEDESCRIPTIONCLKClockThe system clock in

19、put. All other inputs are registered to the SDRAM on the rising edge of CLK.CKEClock EnableControls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refreshCSChip SelectEnables or disables all inputs except CLK, CKE and DQMBA0, BA1Bank

20、 AddressSelects bank to be activated during RAS activity Selects bank to be read/written during CAS activityA0 A11AddressRow Address : RA0 RA11, Column Address : CA0 CA7 Auto-precharge flag : A10 RAS, CAS, WERow Address Strobe,Column Address Strobe, Write EnableRAS, CAS and WE define the operation R

21、efer function truth table for detailsDQM03Data Input/Output MaskControls output buffers in read mode and masks input data in write modeDQ0 DQ31Data Input/OutputMultiplexed data input / output pinVDD/VSSPower Supply/GroundPower supply for internal circuits and input buffersVDDQ/VSSQData Output Power/

22、GroundPower supply for output buffersNCNo ConnectionNo connectionDQ26DQ24VSSVDDDQ23DQ21DQ28VDDQVSSQVDDQVSSQDQ19VSSQDQ27DQ25DQ22DQ20VDDQVSSQDQ29DQ30DQ17DQ18VDDQVDDQDQ31NCNCDQ16VSSQVSSDQM3A3A2DQM2VDDA4A5A6A10A0A1Top ViewA7A8NCNCBA1A11CLKCKEA9BA0/CS/RASDQM1NCNC/CAS/WEDQM0VDDQDQ8VSSVDDDQ7VSSQVSSQDQ10DQ9

23、DQ6DQ5VDDQVSSQDQ12DQ14DQ1DQ3VDDQDQ11VDDQVSSQVDDQVSSQDQ4DQ13DQ15VSSVDDDQ0DQ2HY57V283220(L)T(P) / HY5V22(L)F(P)FUNCTIONAL BLOCK DIAGRAM1Mbit x 4banks x 32 I/O Synchronous DRAM1Mx32 Bank 3CLK1M x32 Bank2Row ActiveCKE1M x32 Bank1CS1M x32 Bank0DQ0DQ1RASMemory CellCASArrayWE DQM0 DQM1 DQM2DQM3Column Activ

24、eDQ30DQ31Y decoderBank SelectA0A1A11BA0 BA1Pipe Line ControlRev. 0.9 / July 20045I/O Buffer & LogicSense AMP & I/O GateX decoder X decoderX decoderX decoderAddress buffersState MachineData Out ControlMode RegisterCAS LatencyBurst CounterAddress RegisterColumn Add CounterColumn Pre DecoderRow PreDeco

25、derSelf Refresh Logic & Timer Refresh CounterHY57V283220(L)T(P) / HY5V22(L)F(P)ABSOLUTE MAXIMUM RATINGSNote : Operation at above absolute maximum rating can adversely affect device reliabilityDC OPERATING CONDITION (TA=0 to 70C)Note :1. All voltages are referenced to VSS = 0V2. IH (max) is acceptabl

26、e 5.6V AC pulse width with 3ns of duration with no input clamp diodes 3.VIL (min) is acceptable -2.0V AC pulse width with 3ns of duration with no input clamp diodesAC OPERATING CONDITION (TA=0 to 70C, 3.0V VDD 3.6V, VSS=0V - Note1)Note :1.Output load to measure access times is equivalent to two TTL

27、gates and one capacitor (30pF) For details, refer to AC/DC output load circuitRev. 0.9 / July 20046ParameterSymbolValueUnitNoteAC input high / low level voltageVIH / VIL2.4/0.4VInput timing measurement reference level voltageVtrip1.4VInput rise / fall timetR / tF1nsOutput timing measurement referenc

28、e levelVoutref1.4VOutput load capacitance for access time measurementCL30pF1ParameterSymbolMinTyp.MaxUnitNotePower Supply VoltageVDD, VDDQ3.03.33.6V1Input high voltageVIH2.03.0VDDQ + 0.3V1,2Input low voltageVIL- 0.300.8V1,3ParameterSymbolRatingUnitAmbient TemperatureTA0 70CStorage TemperatureTSTG-55

29、 125CVoltage on Any Pin relative to VSSVIN, VOUT-1.0 4.6VVoltage on VDD relative to VSSVDD, VDDQ-1.0 4.6VShort Circuit Output CurrentIOS50mAPower DissipationPD1WSoldering Temperature TimeTSOLDER260 10 C SecHY57V283220(L)T(P) / HY5V22(L)F(P)CAPACITANCE ( HY57V283220T Series) (TA=25C, f=1MHz, VDD=3.3V

30、)OUTPUT LOAD CIRCUITVtt=1.4VVtt=1.4VRT=500 WRT=50 WOutputZ0 = 50WOutput 30pF30pFDC Output Load CircuitAC Output Load CircuitDC CHARACTERISTICS I (DC operating conditions unless otherwise noted)Note :1.VIN = 0 to 3.6V, All other pins are not under test = 0V 2.DOUT is disabled, VOUT=0 to 3.6VRev. 0.9

31、/ July 20047ParameterSymbolMin.MaxUnitNoteInput leakage currentILI-11uA1Output leakage currentILO-11uA2Output high voltageVOH2.4-VIOH = -2mAOutput low voltageVOL-0.4VIOL = +2mAParameterPinSymbolMinMaxUnitInput capacitanceCLKCI12.54.0pFA0 A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM03CI22.54.0pFData inp

32、ut / output capacitanceDQ0 DQ31CI/O4.06.5pFHY57V283220(L)T(P) / HY5V22(L)F(P)DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)Note :1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time

33、) is shown at AC CHARACTERISTICS II 3.HY57V283220T(P)(HY5V22F(P)-5/55/6/7/H/8/P/S4.HY57V283220LT(P)(HY5V22LF(P)-5/55/6/7/H/8/P/SRev. 0.9 / July 20048ParameterSymbolTest ConditionSpeedUnitNote-5-55-6-7-H-8-PSOperating CurrentPrecharge Standby Current in power down modeIDD1IDD2PBurst length=1, One ban

34、k active tRC tRC(min), IOL=0mACKE VIL(max), tCK = 10ns1201201101001001009090mAmA12IDD2PSCKE VIL(max), tCK = 1Precharge Standby Current in non power down modeActive Standby Current in power down modeActive Standby Currentin non power down modeIDD2NIDD2NSIDD3P IDD3PSIDD3NIDD3NSCKE VIH(min), CS VIH(min

35、),tCK = 10ns Input signals are changed one time during 2clks. All other pins VDD- 0.2V or 0.2VCKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 10ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min),tCK = 10ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.

36、2VCKE VIH(min), tCK = Input signals are stable.149761713mAmAmABurst Mode Operating CurrentIDD4ttCK tCK(min), IOL=0mAAll banks activeCL=3CL=2230-220-200-180-180-150-130130130130mA1Auto Refresh CurrentIDD5tRC tRC(min), All banks active170160150140140140140140mA2Self Refresh CurrentIDD6CKE 0.2V2mA30.84

37、HY57V283220(L)T(P) / HY5V22(L)F(P)AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)-5-55-6-7-H-8-P-SParameterSymbolUnitNoteMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxCAS Latency = 3tCK355.5677.581010nsSystem clock cycle time10001000100010001000100010001000CAS Latency = 2tCK2

38、1010101010-101012nsClock high pulse widthtCHW2-2.25-2.5-3-3-3-3-3-ns1Clock low pulse widthtCLW2-2.25-2.5-3-3-3-3-3-ns1CAS Latency = 3tAC3-4.5-5-5.5-5.5-5.5-6-6-6nsAccess time from clock2CAS Latency = 2tAC2-6-6-6-6-6-6-6-6nsData-out hold timetOH1.5-2-2-2-2-2-2-2-ns3Data-Input setup timetDS1.5-1.5-1.5

39、-1.75-1.75-2-2-2-ns1Data-Input hold timetDH1-1-1-1-1-1-1-1-ns1Address setup timetAS1.5-1.5-1.5-1.75-1.75-2-2-2-ns1Address hold timetAH1-1-1-1-1-1-1-1-ns1CKE setup timetCKS1.5-1.5-1.5-1.75-1.75-2-2-2-ns1CKE hold timetCKH1-1-1-1-1-1-1-1-ns1Command setup timetCS1.5-1.5-1.5-1.75-1.75-2-2-2-ns1Command ho

40、ld timetCH1-1-1-1-1-1-1-1-ns1CLK to data output in low Z-timetOLZ1-1-1-1-1-1-1-1-nsCAS Latency = 3tOHZ3-4.5-5-5.5-5.5-5.5-6-6-6nsCLK to data output in high Z-timeCAS Latency = 2tOHZ2-6-6-6-6-6-6-6-6nsNote :1. Assume tR / tF (input rise and fall time ) is 1ns2. Access times to be measured with input

41、signals of 1v/ns edge rate, 0.8v to 2.0v 3.Data-out hold time to be measured under 30pF load condition, without Vt terminationRev. 0.9 / July 20049HY57V283220(L)T(P) / HY5V22(L)F(P)AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)Note :1. A new command can be given tRRC after se

42、lf refresh exitRev. 0.9 / July 200410ParameterSymbol-5-55-6-7-H-8-P-SUnitNoteMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxRAS cycle timeOperationAuto RefreshtRC tRRCtRCD555515-555516.5-606018-636320-636320-646420-707020-707020-ns nsnsRAS to CAS delayRAS active timeRAS precharge timetRAStRP38.7151

43、00K-38.716.5100K-4218100K-4220100K-4220100K-4820100K-5020100K-5020100K-nsnsRAS to RAS bank active delay CAS to CAS delayWrite command to data-in delaytRRD tCCDtWTL210-210-210-210-210-210-2010-2010-CLK CLKCLKData-in to precharge command Data-in to active commandDQM to data-out Hi-ZtDPL tDALtDQZ142-142-142-142-142-142-142-142-CLK CLKCLKDQM to data-in maskMRS to new commandtDQM tMRDtPROZ3023-023-023-023-023-023-023-023-CLK CLKCLKPrecharge to data output Hi-ZCAS Latency = 3CAS Latency = 2tPROZ2tPDE21-21-21-21-21-21-21-21-CLKCLKPower down ex