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第五章 习题答案1. 画出与阵列编程点解:2. 画出或阵列编程点 解: 3. 与、或阵列均可编程,画出编程点。解;4. 4变量LUT编程解:5. 用VHDL写出4输入与门解: 源代码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY and4 IS PORT (a,b,c,d:IN STD_LOGIC; x:OUT STD_LOGIC); END and4; ARCHITECTURE and4_arc OF and4 IS BEGIN xa AND b AND c AND d; END and4_arc; 6. 用VHDL写出4输入或门解: 源代码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or4 IS PORT (a,b,c,d:IN STD_LOGIC; x:OUT STD_LOGIC); END or4; ARCHITECTURE or4_arc OF or4 IS BEGIN xa OR b OR c OR d; END or4_arc;7. 用VHDL写出SOP表达式解: 源代码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY sop IS PORT (a,b,c,d,e,f:IN STD_LOGIC; x:OUT STD_LOGIC); END sop; ARCHITECTURE sop_arc OF sop IS BEGIN x(a AND b) OR (c AND d) OR (e AND f); END sop_arc;8. 用VHDL写出布尔表达式解: 源代码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY boolean IS PORT (a,b,c:IN STD_LOGIC; f:OUT STD_LOGIC); END boolean ; ARCHITECTURE boolean_arc OF boolean IS BEGIN f(a OR (NOT b) OR c) AND (a OR b OR (NOT c) AND (NOT a) OR (NOT b) OR (NOT c); END boolean_arc;9. 用VHDL结构法写出SOP表达式解: 源代码: 三输入与非门的逻辑描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand3 IS PORT (a,b,c:IN STD_LOGIC; x:OUT STD_LOGIC); END nand3; ARCHITECTURE nand3_arc OF nand3 IS BEGIN xNOT (a AND b AND c); END nand3_arc;顶层结构描述文件 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY sop IS PORT (in1,in2,in3,in4,in5,in6,in7,in8,in9:IN STD_LOGIC; out4:OUT STD_LOGIC); END sop; ARCHITECTURE sop_arc OF sop IS COMPONENT nand3 PORT (a,b,c:IN STD_LOGIC; x:OUT STD_LOGIC); END COMPONENT; SIGNAL out1,out2,out3:STD_LOGIC; BEGIN u1:nand3 PORT MAP (in1,in2,in3,out1); u2:nand3 PORT MAP (in4,in5,in6,out2); u3:nand3 PORT MAP (in7,in8,in9,out3); u4:nand3 PORT MAP (out1,out2,out3,out4); END sop;10. 用VHDL数据流法写出SOP表达式解: 源代码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY sop IS PORT (in1,in2,in3,in4,in5,in6,in7,in8,in9:IN STD_LOGIC; out4:OUT STD_LOGIC); END sop; ARCHITECTURE sop_arc OF sop IS BEGIN out4(in1 AND in2 AND in3) OR (in4 AND in5 AND in6 ) OR (in7 AND in8 AND in9); END sop_arc;13. 用VHDL设计38译码器 解: 源代码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY decoder_3_to_8 IS PORT (a,b,c,g1,g2a,g2b:IN STD_LOGIC; y:OUT STD_LOGIC _VECTOR(7 downto 0); END decoder_3_to_8; ARCHITECTURE rt1 OF decoder_3_to_8 IS SIGNAL indata:STD_LOGIC _VECTOR(2 downto 0); BEGIN indatac & b & a; PROCESS(indata,g1,g2a,g2b) BEGIN IF(g11 AND g2a0 AND g2b0)THEN CASE indata IS WHEN 000y11111110; WHEN 001y11111101; WHEN 010y11111011; WHEN 011y11110111; WHEN 100y11101111; WHEN 101y11011111; WHEN 110y10111111; WHEN othersy01111111; END CASE; ELSE y11111111; END IF; END PROCESS; END rt1;14. 用VHDL设计七段显示译码器 解: 源代码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY segment7 IS PORT (xin:IN STD_LOGIC _VECTOR(3 downto 0); lt,rbi:IN STD_LOGIC; yout:OUT STD_LOGIC _VECTOR(6 downto 0);birbo:INOUT STD_LOGIC); END segment7; ARCHITECTURE seg7448 OF segment7 IS SIGNAL sig_xin: STD_LOGIC _VECTOR(3 downto 0); BEGIN sig_xinxin; PROCESS(sig_xin,lt,rbi,birbo) BEGIN IF(birbo0)THEN yout0000000; ELSIF (lt0)THEN yout1111111; birbo1; ELSIF (rbi0 AND sig_xin0000)THEN yout0000000; birbo0; ELSIF (rbi1 AND sig_xin0000)THEN yout1111110; birbo1; ELSE birbo1; CASE sig_xin IS WHEN 0001yout0110000; WHEN 0010yout1101101; WHEN 0011yout1111001; WHEN 0100yout0110011; WHEN 0101yout1011011; WHEN 0110yout0011111; WHEN 0111yout1110000; WHEN 1000yout1111111; WHEN 1001yout1110011; WHEN othersyout0100011; END CASE; END IF; END PROCESS; END seg7448;15. 用VHDL设计8/3优先编码器 解: 源代码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY priorityencoder IS PORT (din:IN STD_LOGIC _VECTOR(7 downto 0); ei:IN STD_LOGIC; yout:OUT STD_LOGIC _VECTOR(2 downto 0);eo,gs:OUT STD_LOGIC); END priorityencoder; ARCHITECTURE cod74148 OF priorityencoder IS BEGIN PROCESS(ei,din) BEGIN IF(ei1)THEN yout111; eo1; gs1; ELSE IF (din(7)0 ) THEN yout000; eo1; gs0;ELSIF (din(6)0 ) THEN yout 001; eo1; gs0;ELSIF (din(5)0 ) THEN yout010; eo1; gs0;ELSIF (din(4)0 ) THEN yout011; eo1; gs0;ELSIF (din(3)0 ) THEN yout100; eo1; gs0;ELSIF (din(2)0 ) THEN yout101; eo1; gs0;ELSIF (din(1)0 ) THEN yout110; eo1; gs0;ELSIF (din(0)0 ) THEN yout111; eo1; gs0;ELSIF (din11111111) THEN yout111; eo0; gs1; END IF; END IF; END PROCESS; END cod74148;16. 用VHDL设计BCD码至二进制码转换器。解: 源代码:library ieee;use ieee.std_logic_1164.all;entity bcdtobi isport( bcdcode : IN STD_LOGIC_VECTOR(7 DOWNTO 0); start: in std_logic; qbit : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );end;architecture behavioral of bcdtobi isbeginprocess(start)beginif start=0 thencase bcdcode(7 downto 0) iswhen 00000000=qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)qbit(3 downto 0)=0000;end case;elseqbit(3 downto 0)=0000;end if;end process;end behavioral;17. 用VHDL设计4位寄存器解: 异步复位源代码: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY register_4 IS PORT (clk,r:IN STD_LOGIC;din:IN STD_LOGIC _VECTOR(3 downto 0); qout:OUT STD_LOGIC _VECTOR(3 downto 0); END register_4; ARCHITECTURE rge_arc OF register_4 IS SIGNAL q_temp:STD_LOGIC _VECTOR(3 downto 0); BEGIN PROCESS(clk,r) BEGIN IF(r1)THEN q_temp0000;ELSIF (clkevent AND clk1 ) THEN q_tempdin; END IF; qoutq_temp; END PROCESS; END rge_arc;18. 用VHDL设计4位双向移位寄存器解: s1、s0控制工作方式,dsl为左移数据输入,dsr为右移数据输入。源代码:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY shiftreg IS PORT (clk,r,dsr,dsl:IN STD_LOGIC;s1,s0:IN STD_LOGIC;-function selectdin:IN STD_LOGIC _VECTOR(3 downto 0);-data in qout:OUT STD_LOGIC _VECTOR(3 downto 0);-data outEND shiftreg;ARCHITECTURE ls74194 OF shiftreg ISSIGNAL iq: STD_LOGIC _VECTOR(3 downto 0);SIGNAL s:STD_LOGIC _VECTOR(1 downto 0);BEGIN ss1 & s0; PROCESS(clk,r) BEGIN IF(r0)THEN iq0000;ELSIF (clkevent AND clk1 ) THENCASE s IS WHEN 00null; WHEN 01iqdsr & din(3 downto 1);-right WHEN 10iqdin(2 downto 0)& dsl;-left WHEN 11iqdin;-load WHEN othersnull; END CASE; END IF; qoutiq; END PROCESS;END ls74194;19. 用VHDL设计8421码十进制加法计数器解: 异步清零,同步置数源代码:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count10 IS PORT (clk,clr,load:IN STD_LOGIC; din:IN STD_LOGIC _VECTOR(3 downto 0); co:OUT STD_LOGIC; qout:OUT STD_LOGIC _VECTOR(3 downto 0);END count10;ARCHITECTURE count10_arch OF count10 ISSIGNAL iq: STD_LOGIC _VECTOR(3 downto 0);BEGINPROCESS(clr,clk,load)BEGIN IF(clr0)THEN iq0000;ELSIF (clkevent AND clk1 ) THENIF(load0)THEN iqdin;ELSIF(iq9)THEN iq0000; ELSE iqiq+1; END IF; END IF; qoutiq; END PROCESS; co1 WHEN iq1001 ELSE 0;END count10_arch;20用VHDL设计可逆格雷码计数器解: 源代码:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY gray_count IS PORT (clk,y:IN STD_LOGIC; qout:OUT STD_LOGIC _VECTOR(2 downto 0);END gray_count;ARCHITECTURE arch_gray OF gray_count ISSIGNAL iq: STD_LOGIC _VECTOR(2 downto 0);BEGIN PROCESS(clk) BEGIN IF (clkevent AND clk1 ) THENIF(y1)THEN CASE iq IS WHEN 000iq001; WHEN 001iq011; WHEN 011iq010; WHEN 010iq110; WHEN 110iq111; WHEN 111iq101; WHEN 101iq100; WHEN othersiq000; END CASE; END IF;IF(y0)THEN CASE iq IS WHEN 000iq100; WHEN 100iq101; WHEN 101iq111; WHEN 111iq110; WHEN 110iq010; WHEN 010iq011; WHEN 011iq001; WHEN othersiq000; END CASE; END IF; END IF;qoutiq; END PROCESS;END arch_gray;2
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