80C51 family programmer guide.pdf

PhilipsSemiconductors80C51familyprogrammersguideandinstructionset80C51Family1March1995PROGRAMMERSGUIDEANDINSTRUCTIONSETMemoryOrganizationProgramMemoryThe80C51hasseparateaddressspacesforprogramanddatamemory.TheProgrammemorycanbeupto64kbyteslong.Thelower4kcanresideon-chip.Figure1showsamapofthe80C51programmemory.The80C51canaddressupto64kbytesofdatamemorytothechip.TheMOVXinstructionisusedtoaccesstheexternaldatamemory.The80C51has128bytesofon-chipRAM,plusanumberofSpecialFunctionRegisters(SFRs).Thelower128bytesofRAMcanbeaccessedeitherbydirectaddressing(MOVdataaddr)orbyindirectaddressing(MOVRi).Figure2showstheDataMemoryorganization.DirectandIndirectAddressAreaThe128bytesofRAMwhichcanbeaccessedbybothdirectandindirectaddressingcanbedividedintothreesegmentsaslistedbelowandshowninFigure3.1.RegisterBanks0-3:Locations0through1FH(32bytes).Thedeviceafterresetdefaultstoregisterbank0.Tousetheotherregisterbanks,theusermustselecttheminsoftware.Eachregisterbankcontainseight1-byteregisters0through7.Resetinitializesthestackpointertolocation07H,anditisincrementedoncetostartfromlocation08H,whichisthefirstregister(R0)ofthesecondregisterbank.Thus,inordertousemorethanoneregisterbank,theSPshouldbeinitializedtoadifferentlocationoftheRAMwhereitisnotusedfordatastorage(i.e.,thehigherpartoftheRAM).2.BitAddressableArea:16byteshavebeenassignedforthissegment,20H-2FH.Eachoneofthe128bitsofthissegmentcanbedirectlyaddressed(0-7FH).Thebitscanbereferredtointwoways,bothofwhichareacceptablebymostassemblers.Onewayistorefertotheiraddress(i.e.,0-7FH).Theotherwayiswithreferencetobytes20Hto2FH.Thus,bits0-7canalsobereferredtoasbits20.0-20.7,andbits8-FHarethesameas21.0-21.7,andsoon.Eachofthe16bytesinthissegmentcanalsobeaddressedasabyte.3.ScratchPadArea:30Hthrough7FHareavailabletotheuserasdataRAM.However,ifthestackpointerhasbeeninitializedtothisarea,enoughbytesshouldbeleftasidetopreventSPdatadestruction.Figure2showsthedifferentsegmentsoftheon-chipRAM.OR60kBYTESEXTERNALANDFFFF10000FFF00004kBYTESINTERNAL64kBYTESEXTERNALFFFF0000SU00567Figure1.80C51ProgramMemory80C51familyprogrammersguideandinstructionsetPhilipsSemiconductors80C51FamilyMarch19952SFRsDIRECTADDRESSINGONLYANDFF807F0064kBYTESEXTERNAL0FFF0000DRIECTANDINDIRECTADDRESSINGINTERNALSU00568Figure2.80C51DataMemorySCRATCHPADAREA8BYTES787068605850484038302820181008007F776F675F574F473F372F271F170F07.7F0.3210BITADDRESSABLESEGMENTREGISTERBANKSSU00569Figure3.128BytesofRAMDirectandIndirectAddressable80C51familyprogrammersguideandinstructionsetPhilipsSemiconductors80C51FamilyMarch19953Table1.80C51SpecialFunctionRegistersSYMBOLDESCRIPTIONDIRECTADDRESSBITADDRESS,SYMBOL,ORALTERNATIVEPORTFUNCTIONMSBLSBRESETVALUEACC*AccumulatorE0HE7E6E5E4E3E2E1E000HB*BregisterF0HF7F6F5F4F3F2F1F000HDPTRDatapointer(2bytes)DPHDatapointerhigh83H00HDPLDatapointerlow82H00HAFAEADACABAAA9A8IE*InterruptenableA8HEAESET1EX1ET0EX00x000000BBFBEBDBCBBBAB9B8IP*InterruptpriorityB8HPSPT1PX1PT0PX0xx000000B8786858483828180P0*Port080HAD7AD6AD5AD4AD3AD2AD1AD0FFH9796959493929190P1*Port190HT2EXT2FFHA7A6A5A4A3A2A1A0P2*Port2A0HA15A14A13A12A11A10A9A8FFHB7B6B5B4B3B2B1B0P3*Port3B0HRDWRT1T0INT1INT0TxDRxdFFHPCON1Powercontrol87HSMODGF1GF0PDIDL0xxxxxxxBD7D6D5D4D3D2D1D0PSW*ProgramstatuswordD0HCYACF0RS1RS0OVP00HSBUFSerialdatabuffer99HxxxxxxxxB9F9E9D9C9B9A9998SCON*Serialcontroller98HSM0SM1SM2RENTB8RB8TIRI00HSPStackpointer81H07H8F8E8D8C8B8A8988TCON*Timercontrol88HTF1TR1TF0TR0IE1IT1IE0IT0TH0Timerhigh08CH00HTH1Timerhigh18DH00HTL0Timerlow08AH00HTL1Timerlow18BH00HTMODTimermode89HGATEC/TM1M0GATEC/TM1M000HNOTES:*Bitaddressable1.BitsGF1,GF0,PD,andIDLofthePCONregisterarenotimplementedontheNMOS8051/8031.80C51familyprogrammersguideandinstructionsetPhilipsSemiconductors80C51FamilyMarch19954F8F0E8E0D8D0C8C0B8B0A8A098908880FFF7EFE7DFD7CFC7BFB7AFA79F978F87TCON8BYTESBITADDRESSABLEP0P1SCONP2IEP3IPPSWACCBSBUFTMODTL0TL1TH0TH1SPDPLDPHPCONSU00570Figure4.SFRMemoryMap80C51familyprogrammersguideandinstructionsetPhilipsSemiconductors80C51FamilyMarch19955ThoseSFRsthathavetheirbitsassignedforvariousfunctionsarelistedinthissection.Abriefdescriptionofeachbitisprovidedforquickreference.FormoredetailedinformationrefertotheArchitectureChapterofthisbook.PSW:PROGRAMSTATUSWORD.BITADDRESSABLE.CYACF0RS1RS0OVPCYPSW.7CarryFlag.ACPSW.6AuxiliaryCarryFlag.F0PSW.5Flag0availabletotheuserforgeneralpurpose.RS1PSW.4RegisterBankselectorbit1(SEENOTE1).RS0PSW.3RegisterBankselectorbit0(SEENOTE1).OVPSW.2OverflowFlag.PSW.1Usableasageneralpurposeflag.PPSW.0Parityflag.Set/clearedbyhardwareeachinstructioncycletoindicateanodd/evennumberof1busintheaccumulator.NOTE:1.ThevaluepresentedbyRS0andRS1selectsthecorrespondingregisterbank.RS1RS0REGISTERBANKADDRESS00000H-07H01108H-0FH10210H-17H11318H-1FHPCON:POWERCONTROLREGISTER.NOTBITADDRESSABLE.SMODGF1GF0PDIDLSMODDoublebaudratebit.IfTimer1isusedtogeneratebaudrateandSMOD=1,thebaudrateisdoubledwhentheSerialPortisusedinmodes1,2,or3.Notimplemented,reservedforfutureuse.*Notimplementedreservedforfutureuse.*Notimplementedreservedforfutureuse.*GF1Generalpurposeflagbit.GF0Generalpurposeflagbit.PDPowerDownBit.SettingthisbitactivatesPowerDownoperationinthe80C51.(AvailableonlyinCMOS.)IDLIdlemodebit.SettingthisbitactivatesIdleModeoperationinthe80C51.(AvailableonlyinCMOS.)If1sarewrittentoPDandIDLatthesametime,PDtakesprecedence.*Usersoftwareshouldnotwrite1storeservedbits.Thesebitsmaybeusedinfuture8051productstoinvokenewfeatures.80C51familyprogrammersguideandinstructionsetPhilipsSemiconductors80C51FamilyMarch19956INTERRUPTS:Touseanyoftheinterruptsinthe80C51Family,thefollowingthreestepsmustbetaken.1.SettheEA(enableall)bitintheIEregisterto1.2.SetthecorrespondingindividualinterruptenablebitintheIEregisterto1.3.BegintheinterruptserviceroutineatthecorrespondingVectorAddressofthatinterrupt.SeeTablebelow.INTERRUPTSOURCEVECTORADDRESSIE00003HTF0000BHIE10013HTF1001BHRI&TI0023HInaddition,forexternalinterrupts,pinsINT0andINT1(P3.2andP3.3)mustbesetto1,anddependingonwhethertheinterruptistobelevelortransitionactivated,bitsIT0orIT1intheTCONregistermayneedtobesetto1.ITx=0levelactivatedITx=1transitionactivatedIE:INTERRUPTENABLEREGISTER.BITADDRESSABLE.Ifthebitis0,thecorrespondinginterruptisdisabled.Ifthebitis1,thecorrespondinginterruptisenabled.EAESET1EX1ET0EX0EAIE.7Disablesallinterrupts.IfEA=0,nointerruptwillbeacknowledged.IfEA=1,eachinterruptsourceisindividuallyenabledordisabledbysettingorclearingitsenablebit.IE.6Notimplemented,reservedforfutureuse.*IE.5Notimplemented,reservedforfutureuse.*ESIE.4Enableordisabletheserialportinterrupt.ET1IE.3EnableordisabletheTimer1overflowinterrupt.EX1IE.2EnableordisableExternalInterrupt1.ET0IE.1EnableordisabletheTimer0overflowinterrupt.EX0IE.0EnableordisableExternalInterrupt0.*Usersoftwareshouldnotwrite1storeservedbits.Thesebitsmaybeusedinfuture80C51productstoinvokenewfeatures.80C51familyprogrammersguideandinstructionsetPhilipsSemiconductors80C51FamilyMarch19957ASSIGNINGHIGHERPRIORITYTOONEORMOREINTERRUPTS:InordertoassignhigherprioritytoaninterruptthecorrespondingbitintheIPregistermustbesetto1.Rememberthatwhileaninterruptserviceisinprogress,itcannotbeinterruptedbyalowerorsamelevelinterrupt.PRIORITYWITHINLEVEL:Prioritywithinlevelisonlytoresolvesimultaneousrequestsofthesameprioritylevel.Fromhightolow,interruptsourcesarelistedbelow:IE0TF0IE1TF1RIorTIIP:INTERRUPTPRIORITYREGISTER.BITADDRESSABLE.Ifthebitis0,thecorrespondinginterrupthasalowerpriorityandifthebitis1thecorrespondinginterrupthasahigherpriority.PSPT1PX1PT0PX0IP.7Notimplemented,reservedforfutureuse.*IP.6Notimplemented,reservedforfutureuse.*IP.5Notimplemented,reservedforfutureuse.*PSIP.4DefinestheSerialPortinterruptprioritylevel.PT1IP.3DefinestheTimer1interruptprioritylevel.PX1IP.2DefinesExternalInterrupt1prioritylevel.PT0IP.1DefinestheTimer0interruptprioritylevel.PX0IP.0DefinestheExternalInterrupt0prioritylevel.*Usersoftwareshouldnotwrite1storeservedbits.Thesebitsmaybeusedinfuture80C51productstoinvokenewfeatures.80C51familyprogrammersguideandinstructionsetPhilipsSemiconductors80C51FamilyMarch19958TCON:TIMER/COUNTERCONTROLREGISTER.BITADDRESSABLE.TF1TR1TF0TR0IE1IT1IE0IT0TF1TCON.7Timer1overflowflag.SetbyhardwarewhentheTimer/Counter1overflows.Clearedbyhardwareasprocessorvectorstotheinterruptserviceroutine.TR1TCON.6Timer1runcontrolbit.Set/clearedbysoftwaretoturnTimer/Counter1ON/OFF.TF0TCON.5Timer0overflowflag.SetbyhardwarewhentheTimer/Counter0overflows.Clearedbyhardwareasprocessorvectorstotheserviceroutine.TR0TCON.4Timer0runcontrolbit.Set/clearedbysoftwaretoturnTimer/Counter0ON/OFF.IE1TCON.3ExternalInterrupt1edgeflag.SetbyhardwarewhenExternalInterruptedgeisdetected.Clearedbyhardwarewheninterruptisprocessed.IT1TCON.2Interrupt1typecontrolbit.Set/clearedbysoftwaretospecifyfallingedge/lowleveltriggeredExternalInterrupt.IE0TCON.1ExternalInterrupt0edgeflag.SetbyhardwarewhenExternalInterruptedgedetected.Clearedbyhardwarewheninterruptisprocessed.IT0TCON.0Interrupt0typecontrolbit.Set/clearedbysoftwaretospecifyfallingedge/lowleveltriggeredExternalInterrupt.TMOD:TIMER/COUNTERMODECONTROLREGISTER.NOTBITADDRESSABLE.GATEC/TM1M0GATEC/TM1M0Timer1Timer0GATEWhenTRx(inTCON)issetandGATE=1,TIMER/COUNTERxwillrunonlywhileINTxpinishigh(hardwarecontrol).WhenGATE=0,TIMER/COUNTERxwillrunonlywhileTRx=1(softwarecontrol).C/TTimerorCounterselector.ClearedforTimeroperation(inputfrominternalsystemclock).SetforCounteroperation(inputfromTxinputpin).M1Modeselectorbit.(NOTE1)M0Modeselectorbit.(NOTE1)NOTE1:M1M0OperatingMode00013-bitTimer(8048compatible)01116-bitTimer/Counter1028-bitAuto-ReloadTimer/Counter113(Timer0)TL0isan8-bitTimer/CountercontrolledbythestandartTimer0controlbits.TH0isan8-bitTimerandiscontrolledbyTimer1controlbits.113(Timer1)Timer/Counter1stopped.80C51familyprogrammersguideandinstructionsetPhilipsSemiconductors80C51FamilyMar