EDA课程设计-DDS信号源

宁波理工学院宁波理工学院EDA课程设计题目DDS信号源一．函数信号发生器简介函数信号发生器在生产实践和科技领域有着广泛的应用。本设计是采用了EDA技术设计的函数信号发生器。此函数信号发生器的实现是基于VHDL语言描述各个波形产生模块，然后在QuartusⅡ软件上实现波形的编译，仿真和下载到Cyclone芯片上。整个系统由波形产生模块和波形选择模块两个部分组成。最后经过QuartusⅡ软件仿真，证明此次设计可以输出正弦波、方波、三角波等规定波形，并能根据波形选择模块的设定来选择波形输出。二．实验软件QuartusⅡ简介QuartusII是Alera公司推出的一款功能强大，兼容性最好的EDA工具软件。该软件界面友好、使用便捷、功能强大，是一个完全集成化的可编程逻辑设计环境，具有开放性、与结构无关、多平台完全集成化丰富的设计库、模块化工具、支持多种硬件描述语言及有多种高级编程语言接口等特点。QuartusII是Altera公司推出的CPLD/FPGA开发工具，QuartusII提供了完全集成且与电路结构无关的开发包环境，具有数字逻辑设计的全部特性，包括：可利用原理图、结构框图、VerilogHDL、AHDL和VHDL完成电路描述，并将其保存为设计实体文件；芯片平面布局连线编辑；功能强大的逻辑综合工具；完备的电路功能仿真与时序逻辑仿真工具；定时/时序分析与关键路径延时分析；可使用SignalTapII逻辑分析工具进行嵌入式的逻辑分析；支持软件源文件的添加和创建，并将它们链接起来生成编程文件；使用组合编译方式可一次完成整体设计流程；自动定位编译错误；高效的期间编程与验证工具；可读入标准的EDIF网表文件、VHDL网表文件和Verilog网表文件；能生成第三方EDA软件使用的VHDL网表文件和Verilog网表文件。三．设计主要任务及要求一．波形选择：通过按键选择不同的输出波形。二．波形发生：通过软件实现各类波形的产生。三．波形频率控制：通过按键实现对输出波形频率的控制四．总体设计方案函数信号发生器主要由波形选择部分，波形发生部分和输出部分组成，其硬件结构图如下图。五．电路图六．单元电路设计一．频率控制模块代码LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; USEIEEE.STD_LOGIC_UNSIGNED.ALL; ENTITYFREQUENCYIS PORT(CLK:INSTD_LOGIC; A:INSTD_LOGIC_VECTOR(4DOWNTO0);--设置A的初值 FOUT:OUTSTD_LOGIC); END; ARCHITECTUREoneOFFREQUENCYIS SIGNALFULL:STD_LOGIC; BEGIN P_REG:PROCESS(CLK) VARIABLECNT1:STD_LOGIC_VECTOR(4DOWNTO0); BEGIN IFCLK'EVENTANDCLK='1'THEN IFCNT1="11111"THEN CNT1:=A;--当CNT1计数计满时，输入数据D被同步预置给计数器CNT1 FULL<='1';--同时使溢出标志信号FULL输出为高电平 ELSECNT1:=CNT1+1;--否则继续作加1计数 FULL<='0';--且输出溢出标志信号FULL为低电平 ENDIF; ENDIF; ENDPROCESSP_REG; P_DIV:PROCESS(FULL) VARIABLECNT2:STD_LOGIC; BEGIN IFFULL'EVENTANDFULL='1'THEN CNT2:=NOTCNT2;--如果溢出标志信号FULL为高电平，D触发器输出取反 IFCNT2='1'THENFOUT<='1'; ELSEFOUT<='0'; ENDIF; ENDIF; ENDPROCESSP_DIV; END;模块元件图二．按键选择模块代码LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYBUTTONISPORT(d:INSTD_LOGIC_VECTOR(2DOWNTO0);a,b,c:OUTSTD_LOGIC);END;ARCHITECTUREONEOFBUTTONISBEGINPROCESS(d)BEGINCASEdISWHEN"000"=>NULL;WHENOTHERS=>a<=d(0);--dltb<=d(1);--sqrc<=d(2);--sin ENDCASE;ENDPROCESS;END;模块元件图三．三角波信号产生模块代码libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitydeltaisport(clk:instd_logic;clr:instd_logic;q:outstd_logic_vector(7downto0));enddelta;architectureoneofdeltaisbeginprocess(clk,clr)variablenum:std_logic_vector(7downto0);variableff:std_logic;beginifclr='0'thennum:="00000000";elseifclk'eventandclk='1'then--时钟信号有上升沿时有效ifff='0'thenifnum="11111000"thenff:='1';elsenum:=num+8;endif;--以上，ff=0时，上升，直至num加到11111000时，使ff=1elseifnum="00000111"thennum:="00000000";ff:='0';elsenum:=num-8;--以上，ff=1时，下降，直至num减到00000111时，使ff=0endif;endif;endif;endif;q<=num;--每一次脉冲，将num的值给q以输出endprocess;end;模块元件图四．方波信号产生模块代码libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityaquareisport(clk:instd_logic;clr:instd_logic;q:outstd_logic_vector(7downto0));endaquare;architectureoneofaquareissignalff:bit;beginp1:process(clk,clr)variablenum:std_logic_vector(5downto0);beginifclr='0'thenff<='0';elseifclk'eventandclk='1'then--当时钟脉冲有一个上升沿ifnum<31thennum:=num+1;elsenum:="000000";ff<=notff;--num每次加1，加32次ff取反1次endif;endif;endif;endprocessp1;p2:process(clk,ff)beginifclk'eventandclk='1'thenifff='1'thenq<="11111111";--ff=1时输出高电平elseq<="00000000";--ff=0时输出低电平endif;endif;endprocessp2;end;模块元件图五．正弦波信号产生模块代码libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitysinisport(clk:instd_logic;--正弦信号的相位clr:instd_logic;d:outstd_logic_vector(7downto0));--正弦函数值end;architectureoneofsinis--结构体开始beginprocess(clk,clr)variablenum:std_logic_vector(5downto0);beginifclr='0'thend<="00000000";elseifclk'eventandclk='1'thenifnum="111111"thennum:="000000";--每加到111111时清零elsenum:=num+1;endif;endif;endif;casenumis--四个输入，共有16总相位可能360/64=5.625when"000000"=>d<=CONV_STD_LOGIC_VECTOR(128,8);--每5.625取一个点 when"000001"=>d<=CONV_STD_LOGIC_VECTOR(141,8);--共64个点 when"000010"=>d<=CONV_STD_LOGIC_VECTOR(153,8); when"000011"=>d<=CONV_STD_LOGIC_VECTOR(165,8); when"000100"=>d<=CONV_STD_LOGIC_VECTOR(177,8); when"000101"=>d<=CONV_STD_LOGIC_VECTOR(188,8); when"000110"=>d<=CONV_STD_LOGIC_VECTOR(199,8); when"000111"=>d<=CONV_STD_LOGIC_VECTOR(209,8); when"001000"=>d<=CONV_STD_LOGIC_VECTOR(218,8); when"001001"=>d<=CONV_STD_LOGIC_VECTOR(227,8); when"001010"=>d<=CONV_STD_LOGIC_VECTOR(234,8); when"001011"=>d<=CONV_STD_LOGIC_VECTOR(240,8); when"001100"=>d<=CONV_STD_LOGIC_VECTOR(246,8); when"001101"=>d<=CONV_STD_LOGIC_VECTOR(250,8); when"001110"=>d<=CONV_STD_LOGIC_VECTOR(253,8); when"001111"=>d<=CONV_STD_LOGIC_VECTOR(254,8); when"010000"=>d<=CONV_STD_LOGIC_VECTOR(255,8); when"010001"=>d<=CONV_STD_LOGIC_VECTOR(254,8); when"010010"=>d<=CONV_STD_LOGIC_VECTOR(253,8); when"010011"=>d<=CONV_STD_LOGIC_VECTOR(250,8); when"010100"=>d<=CONV_STD_LOGIC_VECTOR(246,8); when"010101"=>d<=CONV_STD_LOGIC_VECTOR(240,8); when"010110"=>d<=CONV_STD_LOGIC_VECTOR(234,8); when"010111"=>d<=CONV_STD_LOGIC_VECTOR(227,8); when"011000"=>d<=CONV_STD_LOGIC_VECTOR(218,8); when"011001"=>d<=CONV_STD_LOGIC_VECTOR(209,8); when"011010"=>d<=CONV_STD_LOGIC_VECTOR(199,8); when"011011"=>d<=CONV_STD_LOGIC_VECTOR(188,8); when"011100"=>d<=CONV_STD_LOGIC_VECTOR(177,8); when"011101"=>d<=CONV_STD_LOGIC_VECTOR(165,8); when"011110"=>d<=CONV_STD_LOGIC_VECTOR(153,8); when"011111"=>d<=CONV_STD_LOGIC_VECTOR(141,8); when"100000"=>d<=CONV_STD_LOGIC_VECTOR(128,8); when"100001"=>d<=CONV_STD_LOGIC_VECTOR(115,8); when"100010"=>d<=CONV_STD_LOGIC_VECTOR(103,8); when"100011"=>d<=CONV_STD_LOGIC_VECTOR(91,8); when"100100"=>d<=CONV_STD_LOGIC_VECTOR(79,8); when"100101"=>d<=CONV_STD_LOGIC_VECTOR(68,8); when"100110"=>d<=CONV_STD_LOGIC_VECTOR(57,8); when"100111"=>d<=CONV_STD_LOGIC_VECTOR(47,8); when"101000"=>d<=CONV_STD_LOGIC_VECTOR(38,8); when"101001"=>d<=CONV_STD_LOGIC_VECTOR(29,8); when"101010"=>d<=CONV_STD_LOGIC_VECTOR(22,8); when"101011"=>d<=CONV_STD_LOGIC_VECTOR(16,8); when"101100"=>d<=CONV_STD_LOGIC_VECTOR(10,8); when"101101"=>d<=CONV_STD_LOGIC_VECTOR(6,8); when"101110"=>d<=CONV_STD_LOGIC_VECTOR(3,8); when"101111"=>d<=CONV_STD_LOGIC_VECTOR(1,8); when"110000"=>d<=CONV_STD_LOGIC_VECTOR(0,8); when"110001"=>d<=CONV_STD_LOGIC_VECTOR(1,8); when"110010"=>d<=CONV_STD_LOGIC_VECTOR(3,8); when"110011"=>d<=CONV_STD_LOGIC_VECTOR(6,8); when"110100"=>d<=CONV_STD_LOGIC_VECTOR(10,8); when"110101"=>d<=CONV_STD_LOGIC_VECTOR(16,8); when"110110"=>d<=CONV_STD_LOGIC_VECTOR(22,8); when"110111"=>d<=CONV_STD_LOGIC_VECTOR(29,8); when"111000"=>d<=CONV_STD_LOGIC_VECTOR(38,8); when"111001"=>d<=CONV_STD_LOGIC_VECTOR(47,8); when"111010"=>d<=CONV_STD_LOGIC_VECTOR(57,8); when"111011"=>d<=CONV_STD_LOGIC_VECTOR(68,8); when"111100"=>d<=CONV_STD_LOGIC_VECTOR(79,8); when"111101"=>d<=CONV_STD_LOGIC_VECTOR(91,8); when"111110"=>d<=CONV_STD_LOGIC_VECTOR(103,