PS2鼠标键盘协议中英对照、英汉互译、外文翻译.doc

毕业设计(论文)外文资料翻译学 院： 信息工程学院 专 业： 通信工程092 (用外文写)外文出处： 附 件： 1.外文资料翻译译文；2.外文原文。 指导教师评语： 签名： 2013 年4月 26 日附件1：外文资料翻译译文ps2鼠标键盘协议 摘要：ps/2接口总线只使用数据线和时钟线两条导线来实现主机与设备的通讯，采用集电极开路实现了一种双向同步串行协议。在总线空闲时，两条线都是高电平。在这种状态下，设备才允许开始传输数据。主机对总线有最高的控制权，在任何时候通过将时钟线拉低就可以禁止设备通信。关键词：ps/2接口；数据线；时钟线；双向同步串行协议1. 通讯：概述 ps / 2鼠标和键盘实现双向同步串行协议。该总线是“空闲”时，两条线都高（集电极开路）。这是唯一的状态下，键盘/鼠标开始传输数据。主机总线拥有最终控制权，并可能抑制随时沟通拉时钟线低。该设备总是产生时钟信号。如果主机要发送数据时，它必须先抑制通信设备拉动时钟低。主机然后再换低和释放时钟数据。这是“请求发送”状态和信号设备开始产生时钟脉冲。摘要：公交数据=高，时钟=高： 空闲状态。数据=高，时钟=低： 通信抑制。数据=低，时钟=高： 主机请求到发送 所有的数据都发送一个字节的时间的11-12位构成一帧中发送的每个字节。这些位是： 1个起始位。始终为0。 8个数据位，至少显着位第一。 1个校验位（奇校验）。 1个停止位。这始终是1。 1，应答位（仅主机到设备通信）被设置，如果有偶数个1的数据位和复位（0），如果有一个数据位中的1的奇数奇偶校验位。数1的数据位加上校验位总是加起来奇数（奇校验），这是用于错误检测。键盘/鼠标必须检查此位如果不正确的话，它应该作出反应，如果它已收到一个无效的命令。读取从设备发送到主机的数据在时钟信号的下降 边缘上，从主机到设备发送的数据的上升沿读取 时钟的频率必须在范围10 - 16.7千赫。这意味着时钟要高30 - 50微秒低30 - 50微秒.如果你设计一个键盘，鼠标，或主机的模拟器，你应该修改/采样数据线在中间的每一个细胞。即15 - 25微秒后相应的时钟过渡。同样，键盘/鼠标总是产生时钟信号，但主机总是有通信的最终控制权。定时是绝对至关重要的。在这篇文章中我给每一个时间量必须严格遵守。2.通讯：设备到主机 数据和时钟线都是集电极开路。和+5 v的每一行之间的一个电阻连接，所以在总线的空闲状态是高的。当键盘或鼠标要发送信息，它首先检查时钟线，以确保它是在一个较高的逻辑电平。如果不是的话，主机是抑制通信和设备必须缓冲任何将要发送的数据，直到主机释放时钟。时钟线必须持续至少50微秒之前的设备就可以开始传输数据。 正如我在上一节中提到，键盘和鼠标使用一个串行协议与11位帧。这些位是： 1个起始位。始终为0。 8个数据位，至少显着位第一。 1个校验位（奇校验）。 1个停止位。这始终是1。键盘/鼠标写入的数据线位钟为高时，由主机时钟是低时，它是只读的。图2和图3示出了这一点。图2：设备到主机的通信。数据线改变状态时，钟为高时，时钟是低，数据是有效的。 图3：“q”键（15h）从键盘发送到计算机的扫描码。通道a是时钟信号通道b的数据信号。- 的时钟频率为10-16.7千赫。从一个时钟脉冲的上升沿到数据转换的时间必须是至少为5微秒。从数据转换到一个时钟脉冲的下降沿的时间必须是至少5微秒和不大于25微秒。主机可能抑制拉动低时钟线至少100微秒随时沟通。如果传输被禁止前11个时钟脉冲，该设备必须中止当前的传输和准备数据重传的“块”，当主机释放时钟。一个“块”的数据可能是一个品牌代码，断码，设备id，鼠标运动包等，例如，如果键盘被中断，同时发送两个字节的断码的第二个字节，就需要重传两个字节，断码，而不仅仅是一个被打断。如果主机拉时钟低之前，先高到低时钟过渡，或者最后一个时钟脉冲的下降沿后，键盘/鼠标不需要重新传输任何数据。但是，如果新的数据被创建的，需要进行传输时，它会被缓冲，直到主机发行时钟。键盘有一个16字节的缓冲区用于此目的。如果发生价值超过16字节的按键，进一步击键将被忽略，直到缓冲区中有足够的空间。小鼠只存储最新的移动数据包传输。3. 主机到设备的通讯 主机到设备通信数据包被发送一点点不同.首先，ps / 2设备总是产生时钟信号。如果主机要发送数据时，它必须首先把时钟和数据线“请求发送”状态如下： 禁止通信拉动时钟低至少100微秒。 应用“请求发送”拉动数据低，然后释放时钟。设备应该检查此状态下，间隔不超过10毫秒。当设备检测到这种状态下，它会开始产生时钟信号和时钟在8个数据位和1个停止位。主机改变了数据线，仅当在时钟线为低电平时，数据被读时钟为高时，由设备。这是相反的什么occours设备到主机的通信。收到停止位后，设备将承认接收到的字节，使数据线低，产生最后一个时钟脉冲。如果主机不释放数据线后的第11个时钟脉冲，该设备将继续产生时钟脉冲直到数据线被释放（然后设备将产生一个错误。）主机可能中止传输时前11个时钟脉冲应答位时钟线至少100微秒。为了使这个过程变得更容易理解，这里的主机必须遵循的步骤将数据发送到一个ps / 2设备：1）把时钟线至少100微秒 2）把数据线低。3）释放时钟线。4）等待设备把时钟线拉低 5）设置/复位数据线发送第一个数据位 6）等待设备把时钟拉高7）等待设备把时钟拉低8）重复步骤5-7，其他7个数据位，校验位9）释放数据线10）等待设备把数据线拉低11）等待设备把时钟线拉低12）等待设备释放数据线和时钟图3用图形表示，图4的定时显示由主机产生的信号，而生成的ps / 2设备分开。注意时机“确认”位 - 数据改变发生时，时钟线为高（而不是当它是低，是其它11位的情况下的变化。）图3：主机到设备的通讯。 图4：详细的主机到设备通信。 参考图4，有两个时间数量的主机看起来。（a）是所花费的时间的移动设备以开始产生时钟脉冲后，主机最初需要的时钟线为低，它必须是不大于15毫秒。（b）是所花费的时间的数据包要发送，它必须是不大于2毫秒。如果不符合这些时间限制，主机应产生一个错误。立即收到“确认”后，主机可能会带来抑制通信，数据处理，而它的时钟线低。如果由主机发送的命令，需要一个响应，该响应必须不迟于20毫秒接收主机后释放时钟线。如果不会发生这种情况时，主机将生成一个错误。附件2：外文原文（复印件）ps2 mouse and keyboard agreementabstract: ps / 2 interface bus using only two wires of the data and clock lines to host communication with the device, the use of open-collector to achieve a two-way synchronous serial protocol. the two lines are high when the bus is idle. in this state, the device is only allowed to begin transmission of data. the highest level of control over the host bus, device communication can be disabled at any time by the clock line low.keywords: ps / 2 interface; cable; clock line; bidirectional synchronous serial protocolcommunication: general description the ps/2 mouse and keyboard implement a bidirectional synchronous serial protocol. the bus is idle when both lines are high (open-collector). this is the only state where the keyboard/mouse is allowed begin transmitting data. the host has ultimate control over the bus and may inhibit communication at any time by pulling the clock line low. the device always generates the clock signal. if the host wants to send data, it must first inhibit communication from the device by pulling clock low. the host then pulls data low and releases clock. this is the request-to-send state and signals the device to start generating clock pulses.summary: bus statesdata = high, clock = high: idle state.data = high, clock = low: communication inhibited.data = low, clock = high: host request-to-send all data is transmitted one byte at a time and each byte is sent in a frame consisting of 11-12 bits. these bits are:1 start bit. this is always 0. 8 data bits, least significant bit first. 1 parity bit (odd parity). 1 stop bit. this is always 1. 1 acknowledge bit (host-to-device communication only)the parity bit is set if there is an even number of 1s in the data bits and reset (0) if there is an odd number of 1s in the data bits. the number of 1s in the data bits plus the parity bit always add up to an odd number (odd parity.) this is used for error detection. the keyboard/mouse must check this bit and if incorrect it should respond as if it had received an invalid command.data sent from the device to the host is read on the falling edge of the clock signal; data sent from the host to the device is read on the rising edge. the clock frequency must be in the range 10 - 16.7 khz. this means clock must be high for 30 - 50 microseconds and low for 30 - 50 microseconds. if youre designing a keyboard, mouse, or host emulator, you should modify/sample the data line in the middle of each cell. i.e. 15 - 25 microseconds after the appropriate clock transition. again, the keyboard/mouse always generates the clock signal, but the host always has ultimate control over communication.timing is absolutely crucial. every time quantity i give in this article must be followed exactly.communication: device-to-host the data and clock lines are both open collector. a resistor is connected between each line and +5v, so the idle state of the bus is high. when the keyboard or mouse wants to send information, it first checks the clock line to make sure its at a high logic level. if its not, the host is inhibiting communication and the device must buffer any to-be-sent data until the host releases clock. the clock line must be continuously high for at least 50 microseconds before the device can begin to transmit its data. as i mentioned in the previous section, the keyboard and mouse use a serial protocol with 11-bit frames. these bits are: 1 start bit. this is always 0. 8 data bits, least significant bit first. 1 parity bit (odd parity). 1 stop bit. this is always 1.the keyboard/mouse writes a bit on the data line when clock is high, and it is read by the host when clock is low. figures 2 and 3 illustrate this.figure 2: device-to-host communication. the data line changes state when clock is high and that data is valid when clock is low. figure 3: scan code for the q key (15h) being sent from a keyboard to the computer. channel a is the clock signal; channel b is the data signal.- the clock frequency is 10-16.7 khz. the time from the rising edge of a clock pulse to a data transition must be at least 5 microseconds. the time from a data transition to the falling edge of a clock pulse must be at least 5 microseconds and no greater than 25 microseconds. the host may inhibit communication at any time by pulling the clock line low for at least 100 microseconds. if a transmission is inhibited before the 11th clock pulse, the device must abort the current transmission and prepare to retransmit the current chunk of data when host releases clock. a chunk of data could be a make code, break code, device id, mouse movement packet, etc. for example, if a keyboard is interrupted while sending the second byte of a two-byte break code, it will need to retransmit both bytes of that break code, not just the one that was interrupted.if the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data. however, if new data is created that needs to be transmitted, it will have to be buffered until the host releases clock. keyboards have a 16-byte buffer for this purpose. if more than 16 bytes worth of keystrokes occur, further keystrokes will be ignored until theres room in the buffer. mice only store the most current movement packet for transmission.host-to-device communication: the packet is sent a little differently in host-to-device communication.first of all, the ps/2 device always generates the clock signal. if the host wants to send data, it must first put the clock and data lines in a request-to-send state as follows: inhibit communication by pulling clock low for at least 100 microseconds. apply request-to-send by pulling data low, then release clock.the device should check for this state at intervals not to exceed 10 milliseconds. when the device detects this state, it will begin generating clock signals and clock in eight data bits and one stop bit. the host changes the data line only when the clock line is low, and data is read by the device when clock is high. this is opposite of what occours in device-to-host communication.after the stop bit is received, the device will acknowledge the received byte by bringing the data line low and generating one last clock pulse. if the host does not release the data line after the 11th clock pulse, the device will continue to generate clock pulses until the the data line is released (the device will then generate an error.)the host may abort transmission at time before the 11th clock pulse (acknowledge bit) by holding clock low for at least 100 microseconds.to make this process a little easier to understand, heres the steps the host must follow to send data to a ps/2 device:1) bring the clock line low for at least 100 microseconds. 2) bring the data line low. 3) release the clock line. 4) wait for the device to bring the clock line low. 5) set/reset the data line to send the first data bit 6) wait for the device to bring clock high. 7) wait for the device to bring clock low. 8) repeat steps 5-7 for the other seven data bits and the parity bit 9) release the data line. 10) wait for the device to bring data low. 11) wait for the device to bring clock low. 12) wait for the device to release data and clockfigure 3 shows this graphically and figure 4 separates the timing to show which signals are generated by the host, and which are generated by the ps/2 device. notice the change in timing for the ack bit-the data transition occours when the clock line is high (rather than when it is low as is the case for the other 11 bits.)figure 3: host-to-device communication. figure 4: detai