单片机设计外文翻译1.docx

附录a 英文原文1 the serial port interface of the lcd driver icthis section will describe how to control the register value of the lcd driver ic on the ltm.the lcd and touch panel module on the ltm is equipped with a lcd driver ic to support three display resolution and with functions of source driver, serial port interface, timing controller, and power supply circuits. to control these functions, users can use fpga to configure the registers in the lcd driver ic via serial port interface.also, there is an analog to digital converter (adc) on the ltm to convert the analog x/y coordinates of the touch point to digital data and output to fpga through the serial port interface of the adc.both lcd driver ic and adc serial port interfaces are connected to the fpga via the 40-pin expansion header and ide cable.because of the limited number of i/o on the expansion header, the serial interfaces of the lcd driver ic and adc need to share the same clock (adc_dclk) and chip enable (scen)signal i/o on the expansion header. to avoid both the serial port interfaces may interfere with each other when sharing the same clock and chip enable signals, the chip enable signal (cs), which is inputted into the adc will come up with a logic inverter as shown in figure1.1. figure 1.1 the serial interface of the lcd touch panel module and ad7843users need to pay attention controlling the shared signals when designing the serial port interface controller. the detailed register maps of the lcd driver ic are listed in appendix chapter.the specifications of the serial port interface of the lcd driver ic are described below.the lcd driver ic supports a clock synchronous serial interface as the interface to a fpga to enable instruction setting. please notice that in addition to the serial port interface signals, nclk input should also be provided while setting the registers. figure 1.2 and table 1.1 show the frame format and timing diagram of the serial port interface. the lcd driver ic recognizes the start of data transfer on the falling edge of scen input and starts data transfer. when setting instruction, the tpg110 inputs the setting values via sda on the rising edge of input scl.table 1.1 the timing parameters of the serial port interfaceitemsymbolconditionminmaxunitsda setup timets0scen to scl150nsts1sda to scl150nssda hold timeth0scen to scl150nsth1sda to scl150nspulse widthtw1lscl pulse width160nstw1hscl pulse width160nstw2scen pulse idth1.0nsclock duty4060%the first 6 bits (a5 a0) specify the address of the register. the next bit means read/write command. “0” is write command. “1” is read command. then, the next cycle is turn-round cycle. finally, the last 8 bits are for data setting (d7 d0). the address and data are transferred from the msb to lsb sequentially. the data is written to the register of assigned address when “end of transfer” is detected after the 16th scl rising cycles. data is not accepted if there are less or more than 16 cycles for one transaction.figure 1.2 the frame format and timing diagram of the serial port interface2 input timing of the lcd panel display functionthis section will describe the timing specification of the lcd synchronous signals and rgb data.to determine the sequencing and the timing of the image signals displayed on the lcd panel, the corresponding synchronous signals from fpga to the lcd panel should follow the timing specification.figure 2.1 lcd horizontal timing specificationfigure 2.1 illustrates the basic timing requirements for each row (horizontal) that is displayed on the lcd panel. an active-low pulse of specific duration (time thpw in the figure) is applied to the horizontal synchronization (hd) input of the lcd panel, which signifies the end of one row of data and the start of the next. the data (rgb) inputs on the lcd panel are not valid for a time period called the hsync back porch ( thbp ) after the hsync pulse occurs, which is followed by the display area ( thd ). during the data display area the rgb data drives each pixel in turn across the row being displayed. also, during the period of the data display area, the data enable signal (den) must be driven to logic high. finally, there is a time period called the hsync front porch ( thfp ) where the rgb signals are not valid again before the next hsync pulse can occur. the timing of the vertical synchronization (vd) is the same as shown in figure 2.2, except that a vsync pulse signifies the end of one frame and the start of the next, and the data refers to the set of rows in the frame (horizontal timing). table 2.1 and 2.2 show for different resolutions, the durations of time periods thpw , thbp , thd , and thfp for both horizontal and vertical timing. finally, the timing specification of the synchronous signals is shown in the table2.3.table 2.1 lcd horizontal timing parametersparametersymbolpanel resolutionunit800xrgbx480480xrgbx272400xrgbx240nclknclk frequencyfnclk33.298.3nclkhorizontal valid datathd800480400nclk1 horizontal lineth1056525528nclkhsync pulse wildthminthbw1-nclktypmaxhsync back porchthbp21643108nclkhsync front porchthfp40220nclkden enable timetep800480400nclkfigure 2.2 lcd vertical timing specificationtable 2.2 lcd vertical timing parametersparametersymbolpanel resolutionunit800xrgbx480480xrgbx272400xrgbx240hvertical valid datatvd480272240hveritial periodtv525286262hveritical blankingtvbp451422hvsync pulse wildthmintvpw1-htypmaxvsync back porchtvbp351220hvsync front porchtvfp1022hden enable timetden480272240htable 2.3 the timing parameters of the lcd synchronous signalsparametersymbolminunitnclk periodpwclk25nsnclk pulse high periodpwh10nsnclk pulse low periodpwl10nshd,vd,den,data setup timetds5nshd,vd,den,data hold timetdh5ns3 the serial interface of the ad converterthis section will describe how to obtain the x/y coordinates of the touch point from the ad converter.the ltm also equipped with an analog devices ad7843 touch screen digitizer chip. the ad7843 is a 12-bit analog to digital converter (adc) for digitizing x and y coordinates of touch points applied to the touch screen. the coordinates of the touch point stored in the ad7843 can be obtained by the serial port interface. to obtain the coordinate from the adc, the first thing users need to do is monitor the interrupt signal adc_penirq_n outputted from the adc. by connecting a pull high resistor, the adc_penirq_n output remains high normally. when the touch screen connected to the adc is touched via a pen or finger, the adc_penirq_n output goes low, initiating an interrupt to a fpga that can then instruct a control word to be written to the adc via the serial port interface.the control word provided to the adc via the din pin is shown in figure 3.1. this provides the conversion start, channel addressing, adc conversion resolution, configuration, and power-down of the adc. the detailed information on the order and description of these control bits can be found from the datasheet of the adc in the datasheet folder on the ltm system cd-rom.figure 3.1 control register bit function descriptionfigure 3.2 shows the typical operation of the serial interface of the adc. the serial clock provides the conversion clock and also controls the transfer of information to and from the adc. one complete conversion can be achieved with 24 adc_dclk cycles. the detailed behavior of the serial port interface can be found in the datasheet of the adc. note that the clock (adc_dclk) and chip enable signals (scen) of the serial port interface shrae the same signal i/o with lcd driver ic. users should avoid controlling the lcd driver ic and adc at the same time when designing the serial port interface controller. also, because the chip enable signal (scen) inputted to the adc comes up with a logic inverter, the logic level of the scen should be inverse when it is used to control the adc.figure 3.2 conversion timing of the serial port interface4 block diagram of the ephoto designthis section will describe the block diagram of the ephoto demonstration tohelp users in reading the code provided.figure 4.1 shows the block diagram of the ephoto demonstration. as soon as the bit stream is downloaded into the fpga, the register values of the lcd driver ic using to control the lcd display function will be configured by the lcd_spi_controller block, which uses the serial port interface to communicate with the lcd driver ic. meanwhile, the flash_to_sdram_controller block will read the rgb data of one picture stored in the flash, and then write the data into sdram buffer. accordingly, both the synchronous control signals and the picture data stored in the sdram buffer will be sent to the ltm via the lcd_timing_controller block. when users touch ltm screens, the x and y coordinates of the touch point will be obtained by the adc_spi_controller block through the adc serial port interface. then the touch_point_detector block will determine whether these coordinates are in a specific range. if the coordinates fit the range, the touch_point_detector block will control the flash_to_sdram_controller block to read the next or previous pictures data from the flash and repeat the steps as mentioned before to command the ltm to display the next or previous picture.figure 4.1 the block diagram of the ephoto demonstration4 sdram controller simulation modelthe sdram controller design files generated by sopc builder are suitable for both synthesis and simulation. some simulation features are implemented in the hdl using “translate on/off” synthesis directives that make certain sections of hdl code invisible to the synthesis tool. the simulation features are implemented primarily for easy simulation of nios and nios ii processor systems using the modelsim simulator. the sdram controller simulation model is not modelsim specific. however, minor changes may be required to make the model work with other simulators. if you change the simulation directives to create a custom simulation flow, be aware that sopc builder overwrites existing files during system generation. take precautions to ensure your changes are not overwritten. simulating nios ii processor designs for a demonstration of simulation of the sdram controller in the context of nios ii embedded processor systems.5 sdram memory modelthis section describes the two options for simulating a memory model of the sdram chip.6.1 using the generic memory modelif the include a functional memory model the system testbench option is enabled at system generation, sopc builder generates an hdl simulation model for the sdram memory. in the auto-generated system testbench, sopc builder automatically wires this memory model to the sdram controller pins. using the automatic memory model and testbench accelerates the process of creating and verifying systems that use the sdram controller. however, the memory model is a generic functional model that does not reflect the true timing or functionality of real sdram chips. the generic model is always structured as a single, monolithic block of memory. for example, even for a system that combines two sdram chips, the generic memory model is implemented as a single entity.6.2 using the sdram manufacturers memory modelif the include a functional memory model the system testbench option is not enabled, you are responsible for obtaining a memory model from the sdram manufacturer, and manually wiring the model to the sdram controller pins in the system testbench.the following examples show how to connect the sdram controller outputs to an sdram chip or chips. the bus labeled ctl is an aggregate of the remaining signals, such as cas_n, ras_n, cke and we_n. figure 6.1 shows a single 128-mbit sdram chip with 32-bit data. the address, data, and control signals are wired directly from the controller to the chip. the result is a 128-mbit (16-mbyte) memory space.figure 6.2 shows two 64-mbit sdram chips, each with 16-bit data. the address and control signals connect in parallel to both chips. the chips share the chipselect (cs_n) signal. each chip provides half of the 32-bit data bus. the result is a logical 128-mbit (16-mbyte) 32-bit data memory.figure 6.1 single 128-mbit sdram chip with 32-bit datafigure 6.2 two 64-mbit sdram chips each with 16-bit datafigure 6.3 shows two 128-mbit sdram chips, each with 32-bit data. the address, data, and control signals connect in parallel to the two chips. the chipselect bus (cs_n1:0) determines which chip is selected. the result is a logical 256-mbit 32-bit wide memory.figure 6.3. two 128-mbit sdram chips each with 32-bit data6.3 software programming modelthe sdram controller behaves like simple memory when accessed via the avalon-mm interface. there are no software-configurable settings and no memory-mapped registers. no software driver routines are required for a processor to access the sdram controller. clock, pll and timing considerations this section describes issues related to synchronizing signals from the sdram controller core with the clock that drives the sdram chip. during sdram transactions, the address, data, and control signals are valid at the sdram pins for a window of time, during which the sdram clock must toggle to capture the correct values. at slower clock frequencies, the clock naturally falls within the valid window. at higher frequencies, you must compensate the sdram clock to align with the valid window.determine when the valid window occurs either by calculation or by analyzing thesdram pins with an oscilloscope. then use a pll to adjust the phase of the sdram clock so that edges occur in the middle of the valid window. tuning the pll might require trial-and-error effort to align the phase shift to the properties of your target board. for details about the pll circuitry in your target device, refer to the appropriate device family handbook. for details about configuring the plls in altera devices, refer to the altpll megafunction user guide.6.4 factors affecting sdram timingthe location and duration of the window depends on several factors:(1) timing parameters of the device and sdram i/o pins i/o timing parameters vary based on device family and speed grade.(2) pin location on the device i/o pins connected to row routing have different timing than pins connected to column routing.(3) logic options used during the quartus ii compilation logic options such as the fast input register and fast output register logic affect the design fit. the location of logic and registers inside the device affects the propagation delays of signals to the i/o pins.(4) sdram cas latencyas a result, the valid window timing is different for different combinations of fpga and sdram devices. the window depends on the quartus ii software fitting results and pin assignments.6.5 symptoms of an untuned plldetecting when the pll is not tuned correctly might be difficult. data transfers to or from the sdram might not fail universally. for example, individual transfers to the sdram controller might succeed, whereas burst transfers fail. for processor-based systems, if software can perform read or write data to sdram, but cannot run when the code is located in sdram, the pll is probably tuned incorrectly.6.6 estimating the valid signal windowthis section describes how to estimate the location and duration of the valid signal window using timing parameters provided in the sdram datasheet and the quartus ii software compilation report. after finding the window, tune the pll so that sdram clock edges occur exactly in the middle of the window. calculating the window is a two-step process. first, determine by how much time the sdram clock can lag the controller clock, and then by how much time it can lead. after finding the maximum lag and lead values, calculate the midpoint between them.these calculations provide an estimation only. the following delays can also affect proper pll tuning, but are not accounted for by these calculations.(1) signal skew due to delays on the printed circuit board these calculations assume zero skew.(2) delay from the pll clock output nodes to destinations these calculations assume that the delay from the pll sdram-clock output-node to the pin is the same as the delay from the pll controller-clock output-node to the clock inputs in the sdram controller. if these clock delays are significantly different, you must account for this phase shift in your window calculations.附录 b 中文翻译1 从串行端口lcd的接口驱动ic本节将介绍如何控制在ltm上的lcd驱动ic的寄存器值，lcd和触摸屏模块的ltm配备了lcd驱动ic支持三中显示分辨率以及源驱动器、串行接口、时序控制器、电源电路的功能。为了控制这些功能，用户可以通过使用fpga配置串行接口在lcd驱动ic寄存器。此外，还有一个模拟/数字转换器（adc）在ltm将接触点的模拟坐标x/y转换成数字数据并通过adc的串行接口输出到fpga模拟，lcd驱动ic和adc串行接口都要通过40-pin扩展头和ide电缆连接到fpga。由于i/o的扩展头数量有限，在扩展头上lcd驱动ic和adc的串行接口需要共享同一个时钟（adc_dclk）和芯片使能（scen）信号，当共享相同的时钟和芯片使能信号时为了避免两个串行接口相互干扰，输入到adc的片选信号（cs）将提出一个逻辑逆变器，如图1.1所示。图1.1 lcd触摸板模块和ad7843串行连接当设计串行接口控制器时用户需要注意控制信号共享。lcd驱动ic的详细列于附录。lcd驱动ic串行接口的规格描述如下。lcd驱动ic支持时钟同步串行接口作为fpga的一个接口，以实现指令设置。请注意，除了串行端口接口信号，设置寄存器时还应具备nclk输入。图1.2和表1.1显示了帧格式和串行接口时序图。lcd驱动ic识别的数据传输在scen输入的下降沿开始启动。设置指令时，tog110通过sd