通用异步接收发送器外文翻译.docx

外文资料原文 transmitting and receiving serial data the universal asynchronous receiver/transmitter (uart) controller is the key component of the serial communications subsystem of a computer. the uart takes bytes of data and transmits the individual bits in a sequential fashion. at the destination, a second uart re-assembles the bits into complete bytes.serial transmission of digital information (bits) through a single wire or other medium is much more cost effective than parallel transmission through multiple wires. a uart is used to convert the transmitted information between its sequential and parallel form at each end of the link. each uart contains a shift register which is the fundamental method of conversion between serial and parallel forms. the uart usually does not directly generate or receive the external signals used between different items of equipment. typically, separate interface devices are used to convert the logic level signals of the uart to and from the external signaling levels.external signals may be of many different forms. examples of standards for voltage signaling are rs-232, rs-422 and rs-485 from the eia. historically, the presence or absence of current (in current loops) was used in telegraph circuits. some signaling schemes do not use electrical wires. examples of such are optical fiber, irda (infrared), and (wireless) bluetooth in its serial port profile (spp). some signaling schemes use modulation of a carrier signal (with or without wires). examples are modulation of audio signals with phone line modems, rf modulation with data radios, and the dc-lin for power line communication. communication may be full duplex (both send and receive at the same time) or half duplex (devices take turns transmitting and receiving). as of 2008, uarts are commonly used with rs-232 for embedded systems communications. it is useful to communicate between microcontrollers and also with pcs. many chips provide uart functionality in silicon, and low-cost chips exist to convert logic level signals (such as ttl voltages) to rs-232 level signals (for example, maxims max232). asynchronous receive and transmit in asynchronous transmitting, teletype-style uarts send a start bit, five to eight data bits, least-significant-bit first, an optional parity bit, and then one, one and a half, or two stop bits. the start bit is the opposite polarity of the data-lines idle state. the stop bit is the data-lines idle state, and provides a delay before the next character can start. (this is called asynchronous start-stop transmission). in mechanical teletypes, the stop bit was often stretched to two bit times to give the mechanism more time to finish printing a character. a stretched stop bit also helps resynchronization. the parity bit can either make the number of one bits between any start/stop pair odd, or even, or it can be omitted. odd parity is more reliable because it assures that there will always be at least one data transition, and this permits many uarts to resynchronize. in synchronous transmission, the clock data is recovered separately from the data stream and no start/stop bits are used. this improves the efficiency of transmission on suitable channels since more of the bits sent are usable data and not character framing. an asynchronous transmission sends no characters over the interconnection when the transmitting device has nothing to send - only idle stop bits; but a synchronous interface must send pad characters to maintain synchronism between the receiver and transmitter. the usual filler is the ascii syn character. this may be done automatically by the transmitting device. usart chips have both synchronous and asynchronous modes. serial to parallel algorithm asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word which are used to synchronize the sending and receiving units. when a word is given to the uart for asynchronous transmissions, a bit called the start bit is added to the beginning of each word that is to be transmitted. the start bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. these two clocks must be accurate enough to not have the frequency drift by more than 10% during the transmission of the remaining bits in the word. (this requirement was set in the days of mechanical teleprinters and is easily met by modern electronic equipment.) after the start bit, the individual bits of the word of data are sent, with the least significant bit (lsb) being sent first. each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits, and the receiver “looks” at the wire at approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. for example, if it takes two seconds to send each bit, the receiver will examine the signal to determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and then examine the value of the next bit, and so on. the sender does not know when the receiver has “looked” at the value of the bit. the sender only knows when the clock says to begin transmitting the next bit of the word.when the entire data word has been sent, the transmitter may add a parity bit that the transmitter generates. the parity bit may be used by the receiver to perform simple error checking. then at least one stop bit is sent by the transmitter. when the receiver has received all of the bits in the data word, it may check for the parity bits (both sender and receiver must agree on whether a parity bit is to be used), and then the receiver looks for a stop bit. if the stop bit does not appear when it is supposed to, the uart considers the entire word to be garbled and will report a framing error to the host processor when the data word is read. the usual cause of a framing error is that the sender and receiver clocks were not running at the same speed, or that the signal was interrupted. regardless of whether the data was received correctly or not, the uart automatically discards the start, parity and stop bits. if the sender and receiver are configured identically, these bits are not passed to the host. if another word is ready for transmission, the start bit for the new word can be sent as soon as the stop bit for the previous word has been sent. because asynchronous data is “self synchronizing”, if there is no data to transmit, the transmission line can be idle. a data communication pulse can only be in one of two states but there are many names for the two states. when on, circuit closed, low voltage, current flowing, or a logical zero, the pulse is said to be in the space condition. when off, circuit open, high voltage, current stopped, or a logical one, the pulse is said to be in the mark condition. a character code begins with the data communication circuit in the space condition. if the mark condition appears, a logical one is recorded otherwise a logical zero.figure 1 shows this format. the start bit is always a 0 (logic low), which is also called a space. the start bit signals the receiving dte that a character code is coming. the next five to eight bits, depending on the code set employed, represent the character. in the ascii code set the eighth data bit may be a parity bit. the next one or two bits are always in the mark (logic high, i.e., 1) condition and called the stop bit(s). they provide a rest interval for the receiving dte so that it may prepare for the next character which may be after the stop bit(s). the rest interval was required by mechanical teletypes which used a motor driven camshaft to decode each character. at the end of each character the motor needed time to strike the character bail (print the character) and reset the camshaft. all operations of the uart hardware are controlled by a clock signal which runs at a multiple (say, 16) of the data rate - each data bit is as long as 16 clock pulses. the receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. if the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. if not, the spurious pulse is ignored. after waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. after the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register is made available (in parallel fashion) to the receiving system. the uart will set a flag indicating new data is available, and may also generate a processor interrupt to request that the host processor transfers the received data. in some common types of uart, a small first-in, first-out (fifo) buffer memory is inserted between the receiver shift register and the host system interface. this allows the host processor more time to handle an interrupt from the uart and prevents loss of received data at high rates. transmission operation is simpler since it is under the control of the transmitting system. as soon as data is deposited in the shift register, the uart hardware generates a start bit, shifts the required number of data bits out to the line,generates and appends the parity bit (if used), and appends the stop bits. since transmission of a single character may take a long time relative to cpu speeds, the uart will maintain a flag showing busy status so that the host system does not deposit a new character for transmission until the previous one has been completed; this may also be done with an interrupt. since full-duplex operation requires characters to be sent and received at the same time, practical uarts use two different shift registers for transmitted characters and received characters. transmitting and receiving uarts must be set for the same bit speed, character length, parity, and stop bits for proper operation. the receiving uart may detect some mismatched settings and set a framing error flag bit for the host system; in exceptional cases the receiving uart will produce an erratic stream of mutilated characters and transfer them to the host system.typical serial ports used with personal computers connected to modems use eight data bits, no parity, and one stop bit; for this configuration the number of ascii character per seconds equals the bit rate divided by 10. history some early telegraph schemes used variable-length pulses (as in morse code) and rotating clockwork mechanisms to transmit alphabetic characters. the first uart-like devices (with fixed-length pulses) were rotating mechanical switches (commutators). these sent 5-bit baudot codes for mechanical teletypewriters, and replaced morse code. later, ascii required a seven bit code. when ibm built computers in the early 1960s with 8-bit characters, it became customary to store the ascii code in 8 bits.gordon bell designed the uart for the pdp series of computers. western digital made the first single-chip uart wd1402a around 1971; this was an early example of a medium scale integrated circuit. an example of an early 1980s uart was the national semiconductor 8250. in the 1990s, newer uarts were developed with on-chip buffers. this allowed higher transmission speed without data loss and without requiring such frequent attention from the computer. for example, the popular national semiconductor 16550 has a 16 byte fifo, and spawned many variants, including the 16c550, 16c650, 16c750, and 16c850. depending on the manufacturer, different terms are used to identify devices that perform the uart functions. intel called their 8251 device a programmable communication interface. mos technology 6551 was known under the name asynchronous communications interface adapter (acia). the term serial communications interface (sci) was first used at motorola around 1975 to refer to their start-stop asynchronous serial interface device, which others were calling a uart. some very low-cost home computers or embedded systems dispensed with a uart and used the cpu to sample the state of an input port or directly manipulate an output port for data transmission. while very cpu-intensive, since the cpu timing was critical, these schemes avoided the purchase of a costly uart chip. the technique was known as a bit-banging serial port. uart models8250, 16450, early 16550: obsolete with 1-byte buffers16550, 16550a, 16c552: 16-byte buffers, tl=1,4,8,14; 115.2 kbps standard, many support 230.4 or 460.8 kbps16650: 32-byte buffers. 460.8 kbps16750: 64-byte buffer for send, 56-byte for receive. 921.6 kbps16850, 16c850: 128-byte buffers. 460.8 kbps or 1.5 mbps16950 hayes esp: 1k-byte buffers. structure a uart usually contains the following components: a clock generator, usually a multiple of the bit rate to allow sampling in the middle of a bit period.input and output shift registerstransmit/receive controlread/write control logictransmit/receive buffers (optional)parallel data bus buffer (optional)first-in, first-out (fifo) buffer memory (optional) special receiver conditions overrun error an overrun error occurs when the uart receiver cannot process the character that just came in before the next one arrives. various uart devices have differing amounts of buffer space to hold received characters. the cpu must service the uart in order to remove characters from the input buffer. if the cpu does not service the uart quickly enough and the buffer becomes full, an overrun error will occur. underrun error an underrun error occurs when the uart transmitter has completed sending a character and the transmit buffer is empty. in asynchronous modes this is treated as an indication that no data remains to be transmitted, rather than an error, since additional stop bits can be appended. this error indication is commonly found in usarts, since an underrun is more serious in synchronous systems. framing error a framing error occurs when the designated start and stop bits are not valid. as the start bit is used to identify the beginning of an incoming character, itacts as a reference for the remaining bits. if the data line is not in the expected idle state when the stop bit is expected, a framing error will occur. parity error a parity error occurs when the number of active bits does not agree with the specified parity configuration of the uart, producing a parity error. because the parity bit is optional, this error will not occur if parity has been disabled. parity error is set when the parity of an incoming data character does not match the expected value. break condition a break condition occurs when the receiver input is at the space level for longer than some duration of time, typically, for more than a character time. this is not necessarily an error, but appears to the receiver as a character of all zero bits with a framing error. some equipment will deliberately transmit the break level for longer than a character as an out-of-band signal. when signaling rates are mismatched, no meaningful characters can be sent, but a long break signal can be a useful way to get the attention of a mismatched receiver to do something (such as resetting itself). unix systems and unix-like systems such as linux can use the long break level as a request to change the signaling rate. baudrate in embedded designs, it is necessary to choose proper oscillator to get correct baud rate with small or no error. some examples of common crystal frequencies and baud rates with no error:18.432 mhz: 300, 600, 1200, 2400, 4800, 9600, 19200 bd22.118400 mhz: 300, 600, 1200, 1800, 2400, 4800, 7200, 9600, 14400, 19200, 38400, 57600, 115200 bd16 mhz: 125000, 500000 bd see alsoasynchronous serial communicationbaudbit ratemodemmorse codeserial communicationserial portusb16550 uart8250 uart external links a tutorial on the rs-232 standard, describing the definition of mark, space and their relationship with negative and positive voltages freebsd tutorials (includes standard signal definitions, history of uart ics, and pinout for commonly used db25 connector)uart tutorial for robotics (contains many practical examples)译文 通用异步接收/发送器 是一种“异步接收器/发射器” ，一块电脑 硬件的转换之间的数据并行和串行的形式。uart常用与其他通信标准，如环境影响评估 rs - 232接口 。uart通常是个（或部分） 积体电路用于串行通讯 ，电脑或外围设备的串行端口 。 uart现在包含在微控制器。 双uart或两个uart 杜阿尔特结合到一个单一芯片中。 许多现代集成电路与现在的uart还可以沟通同步;这些设备被称为通用同步 。 transmitting and receiving serial data 发送和接收串行数据在通用异步接收/发送器（ uart接口）控制器是关键的组成部分，串行通信子系统的一台计算机。 采取的异步字节的数据传输和个人位依次时尚。 在目的地，第二个uart重新组装成完整的bytes.serial位数字信息传输模式（ bits ）通过一个单一的有线或其他媒介更符合成本效益比并行传输，通过多条线路。阿的uart是用来转换之间的信息传播其顺序和并行形式两端的链接。 每个uart接口包含一个移位寄存器这是最根本的方法之间的转换串行和并行的形式。该个uart通常并不直接产生或接收外部信号之间使用不同的设备。通常情况下，单独的接口设备是用来转换逻辑电平信号的uart和来自外部信号的水平。 外部信号可能有许多不同的形式。 实例标准电压信号的rs - 232接口 ， 遥感- 422和rs - 485接口的环境影响评估 。从历史上看，存在或不存在电流（在目前的循环 ）用于电报电路。 一些信令计划不使用电线。.例如是光纤 ，支持irda （ 红外 ）和（无线） 蓝牙在串口简介（许可证） 。 一些计划使用信号调制的载波信号（带或不带线） 。例子有调制的音频信号与电话线调制解调器 ，射频调制数据收音机，以及直流林的电力线载波通信 。通信可能是“全双工” （发送和接收在同一时间）或“半双工” （设备轮流发送和接收） 。截至2008年，个uart常用的rs - 232接口的嵌入式系统的通信。 它是有用的微控制器之间的沟通，并与个人电脑。 许多芯片提供的uart功能硅，和低成本的芯片存在转换逻辑电平信号（如对焦ttl电压） ，以rs - 232接口信号（例如， maxim的max232 ） 。 asynchronous receive and transmit 异步接收和发送在异步传输， 电传式个uart发送“开始”位， 7点55比特的数据，最重要的位第一，一个可选的“平价”位，然后一，一个半或两个“一站式”的位。 起始位是极性相反的数据线的空闲状态。 停车位是数据线的空闲状态，并规定在一段时间后，下一个字符就可以开始。 （这就是所谓的异步起止传输） 。在机械teletypes的“一站式”位往往延伸到2位，以使这一机制更多的时间来完成印刷字符。加长“一站式”位也有助于同步。奇偶校验位可以使一些“一”位之间的任何启动/停