基于简易时钟的设计.doc

简易时钟的设计1. 分频电路的设计-实体名：fen100-功 能：对输入时钟进行24000分频，得到100hz信号，- 作为数码显示管位扫描信号-接 口：clk -时钟输入- qout-100hz输出信号-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fen100 isport(clk:in std_logic; rst:in std_logic; qout:out std_logic);end fen100;architecture behave of fen100 isconstant counter_len:integer:=23999;begin process(clk,rst) variable cnt:integer range 0 to counter_len; begin if(rst=0)then cnt:=0; elsif clkevent and clk=1 then if cnt=counter_len then cnt:=0; else cnt:=cnt+1; end if; case cnt is when 0 to counter_len/2=qoutqoutqoutqout=1; end case; end if; end process;end behave;2.60进制-功 能：60进制计数器-接 口：clk -时钟输入- qout1-个位bcd输出- qout2-十位bcd输出- carry-进位信号输出-library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fen60 is port(clk : in std_logic; rst : in std_logic; qout1 : out std_logic_vector(3 downto 0); qout2 : out std_logic_vector(3 downto 0); carry : out std_logic);end fen60;architecture behave of fen60 issignal tem1:std_logic_vector(3 downto 0);signal tem2:std_logic_vector(3 downto 0);begin process(clk,rst) begin if(rst=0)then tem1=0000; tem2=0000; elsif clkevent and clk=1 then if tem1=1001 then tem1=0000; if tem2=0101 then tem2=0000; carry=1; else tem2=tem2+1; carry=0; end if; else tem1=tem1+1; end if; end if; qout1=tem1; qout2=tem2; end process;end behave; 3.24进制的设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fen24 is port(clk : in std_logic; rst : in std_logic; qout1 : out std_logic_vector(3 downto 0); qout2 : out std_logic_vector(3 downto 0); carry : out std_logic);end fen24;architecture behave of fen24 issignal tem1:std_logic_vector(3 downto 0);signal tem2:std_logic_vector(3 downto 0);begin process(clk,rst) begin if(rst=0)then tem1=0010; tem2=0001; elsif clkevent and clk=1 then if (tem2=0010 and tem1=0011) then tem1=0000; tem2=0000; carry=1; else carry=0; if tem1=1001 then tem1=0000; if tem2=1001 then tem2=0000; else tem2=tem2+1; end if; else tem1=tem1+1; end if; end if; end if; qout1=tem1; qout2=tem2; end process;end behave; 4.数码管显示library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fen24 is port(clk : in std_logic; rst : in std_logic; qout1 : out std_logic_vector(3 downto 0); qout2 : out std_logic_vector(3 downto 0); carry : out std_logic);end fen24;architecture behave of fen24 issignal tem1:std_logic_vector(3 downto 0);signal tem2:std_logic_vector(3 downto 0);begin process(clk,rst) begin if(rst=0)then tem1=0010; tem2=0001; elsif clkevent and clk=1 then if (tem2=0010 and tem1=0011) then tem1=0000; tem2=0000; carry=1; else carry=0; if tem1=1001 then tem1=0000; if tem2=1001 then tem2=0000; else tem2=tem2+1; end if; else tem1=tem1+1; end if; end if; end if; qout1=tem1; qout2=tem2; end process;end behave; 5.数码管显示编码library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fen24 is port(clk : in std_logic; rst : in std_logic; qout1 : out std_logic_vector(3 downto 0); qout2 : out std_logic_vector(3 downto 0); carry : out std_logic);end fen24;architecture behave of fen24 issignal tem1:std_logic_vector(3 downto 0);signal tem2:std_logic_vector(3 downto 0);begin process(clk,rst) begin if(rst=0)then tem1=0010; tem2=0001; elsif clkevent and clk=1 then if (tem2=0010 and tem1=0011) then tem1=0000; tem2=0000; carry=1; else carry=0; i