交通灯控制器.doc

vhdleda gw48 eda/sopcfpga/cpldvhdlquartus 6.0, fpga/cpld, fpga/cpld45540 . 11 . 11. 1 . 11. 2 . 12. . 13. 1 . 12.2 . 24. . 34.1. . 34.2. jtd ctrl . 45. 3jtd time . 56. 4jtd xs . 77. 5jtd light . 98. 6 . 114 . 125 . 126 . 127 . 13/fanteral1. 45540vhdlvhdl,jtd ctrljtd timejtd xsjtd lightjtd ctrl1 khz1 hz1khz1 hzm/fanteral22.2 m = 1sb100100,m = 0m=040 sb100010b1000015sb01010040sb0011005sb100010m=1m=0a 45 40 5b 40 5 45m s 1. 100100 01100010 4022100001 533010100 4044001100 51sab10 /fanteral3 3jtd ctrljtd timejtd xsjtd light22 3 /fanteral4jtd time1hzlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jtd_ctrl isport ( clk :in std_logic;at,bt : in std_logic_vector(7 downto 0);s: out std_logic_vector(1 downto 0);end jtd_ctrl;architecture jtd of jtd_ctrl issignal q :std_logic_vector (1 downto 0);beginprocess(clk,at,bt)beginif clkevent and clk =1 thenif(at =x01)or (bt = x01) then q=q+1; atbtjtd_lightelse q=q;end if;end if;end process;s=q;end jtd;/fanteral5ablibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jtd_time isport( clk : in std_logic;m : in std_logic;s :in std_logic_vector(1 downto 0);at,bt :out std_logic_vector(7 downto 0);end jtd_time;architecture jtd_1 of jtd_time issignal ati : std_logic_vector(7 downto 0):=x01;signal bti : std_logic_vector(7 downto 0):=x01;signal art,agt,ayt : std_logic_vector(7 downto 0);signal brt,bgt,byt : std_logic_vector(7 downto 0);begin art=x45; /fanteral6 agt=x40;ayt=x05;brt=x45;bgt=x40;byt=x05;process (clk,m,s)beginif m = 1 then ati=ati; btiati=art; btibtiati=agt; btiati=ayt;end case;end if;if ati/=x01 then aif ati(3 downto 0)= 0000 thenati(3 downto 0)=1001;ati(7 downto 4)=ati(7 downto 4)-1;else ati(3 downto 0)=ati(3 downto 0)-1;ati(7 downto 4)=ati(7 downto 4);end if;end if;if bti/=x01 then bif bti(3 downto 0)=0000 thenbti(3 downto 0)=1001;bti(7 downto 4)=bti(7 downto 4)-1; /fanteral7 else bti(3 downto 0)=bti(3 downto 0)-1;bti(7 downto 4)=bti(7 downto 4);end if;end if;end if;end if;end process;at=ati;bt=bti;end jtd_1;5 /fanteral8 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jtd_xs isport ( clk1k :in std_logic;at,bt :in std_logic_vector(7 downto 0);led1,led2,led3,led4:out std_logic_vector(3 downto 0);end jtd_xs;architecture jtd_3 of jtd_xs issignal ou1,ou2,ou3,ou4:std_logic_vector(3 downto 0);signal sl:std_logic_vector(1 downto 0);beginprocess(clk1k)beginif clk1kevent and clk1k =1 thenif sl=11 then sl=00; ledelse slou1ou2ou3ou4=at(7 downto 4);end case;end process;led1=ou1; /fanteral9 led2=ou2;led3=ou3;led4=ou4;end jtd_3;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jtd_light isport (m :in std_logic;s : in std_logic_vector(1 downto 0);abl :out std_logic_vector(5 downto 0);6 /fanteral10 end jtd_light;architecture jtd_2 of jtd_light issignal lt: std_logic_vector (5 downto 0);beginprocess (s,m)beginif m =1 then ltltltltlt=001100;end case;end if;end process;abl=lt;end jtd_2;7 /fanteral11gw48 eda/sopc588 /fan