VHDL与数字电路设计PPT课件-第七章 状态机设计.ppt

第七章 状态机设计,vhdl与数字电路设计,本章内容,状态机的电路设计 交通灯控制器设计,1、状态机的电路设计,我们可以用输入信号x和电路状态q来描述时序电路的逻辑功能，这时时序电路称为状态机（state machine）。 根据输出信号和输入信号以及电路状态的关系，状态机可以分为两种：穆尔（moore）型和米利（mealy）型。,y=fx,q,y=fq,米利（mealy）型：,穆尔（moore）型：,（1） more型状态机,输入信号影响状态的转换。,输出信号和输入信号无关。,library ieee; use ieee.std_logic_1164.all; entity more is port( clk,reset: in std_logic; din: in std_logic; op: out std_logic); end more; architecture a of more is type state_type is (s0, s1, s2,s3); signal state: state_type; begin,process (clk,reset) begin if reset = 1 then state if din=1 then state if din=0 then state if din=0 then state if din=1 then state = s0; else state=s1; end if; end case; end if; end if; end process; op=1 when state=s1 else 0; end a;,（2） mealy型状态机,library ieee; use ieee.std_logic_1164.all; entity mealy is port( clk,reset: in std_logic; -clock din: in std_logic; op: out std_logic); end mealy; architecture a of mealy is type state_type is (s0, s1, s2,s3); signal state: state_type; begin,process (clk,reset) begin if reset = 1 then state if din=1 then state if din=0 then state if din=0 then state if din=1 then state = s0; else state=s1; end if; end case; end if; end if; end process; op=1 when (state=s0 and din=1) or (state=s1 and din=1) or (state=s3 and din=1) else 0; -输出不仅与状态有关，而且和输入有关。 end a;,2、交通灯控制器的设计,设计一个十字路口交通灯控制器，东西、南北方向有红灯、黄灯、绿灯，持续时间分别为45、5、40秒。,电路框图,交通灯控制流程图,s0,s1,s2,s3,library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity nclight is port(clk : in std_logic; ra,rb,ya,yb,ga,gb : out std_logic ); end nclight; architecture a of nclight is type state is (s0,s1,s2,s3); signal presentstate,nextstate : state; signal tmp1,tmp2 : integer range 0 to 40; signal timeout1,timeout2: std_logic; signal q: std_logic_vector(21 downto 0); signal sec: std_logic; begin,-get 1 hz clock pulse process(clk) begin if clkevent and clk=1 then q=q+1; end if; sec=q(21); -get 1 hz clock pulse end process; timing: process(sec) begin if secevent and sec=1 then if tmp1=39 then timeout1=1; timeout2=0; tmp1=0; else if timeout1=1 then if tmp2=4 then timeout2=1; timeout1=0; tmp2=0; else tmp2=tmp2+1; end if; else tmp1=tmp1+1; end if; end if; end if; end process;,changestate: process(presentstate) begin case presentstate is when s0 = if timeout1=0 then nextstate if timeout2=0 then nextstate=s1; ra=0; ya=1; ga=0; rb=1; yb=0; gb=0; else nextstate=s2; end if;,when s2 = if