数字系统设计与PLD应用答案.doc

1.7、 (1)算法模型(2)数据处理单元(框图)2.10、2.17、流水线操作结构：TS1=18*100+(256-1)*100=2.73*104(ns)顺序算法结构：TS2=256*18*100=4.608*105(ns)显然流水线操作时间短。（若系统输入数据流的待处理数据元素为m个，每一元素运算共计L段，每段历经时间为，则流水线操作算法结构共需运算时间为：T=L+(m-1) 而顺序算法（或并行算法）结构所需运行时间为：mL）2.30、(1).DFF 状态编码A000 B001 C010 D011 E100输出：（2）“一对一”状态分配次态表：NSPS输入条件AAZCXEXBACBCDBZED-E激励方程：输出：3.2、试给出一位全减器的算法描述和数据流描述真值表：xybidbo0000000111010110110110010101001100011111x被减数 y减数 bi低位向本位的借位 d差 bo本位向高位的借位LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY full_sub IS PORT(x, y,bi : IN Std_Logic; d,bo : OUT Std_Logic);END full_sub;算法描述：ARICHITECTURE alg_fs OF full_sub ISBIGIN PROCESS(x,y,bi) BEGIN IF (x=0 AND y=0 AND bi=0 OR x=1 AND y=0 AND bi=1 OR x=1 AND y=1 AND bi=0 ) THEN bo=0; d=0; ELSIF (x=1 AND y=0 AND bi=0 ) THEN bo=0; d=1; ELSIF (x=0 AND y=1 AND bi=1 ) THEN bo=1; d=0; ELSE bo=1; d=1; END IF; END PROCESS c1;END alg_fs;数据流描述：（d=xybi bo=xy+xbi+ybi）ARICHITECTURE dataflow_fs OF full_sub ISBEGIN d=x XOR y XOR bi; bo=(NOT x AND y) OR (NOT x AND bi) OR (y AND bi);END dataflow_ha;3.4、(1).十进制-BCD码编码器，输入、输出均为低电平有效。LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY encoder ISPORT(a : IN Std_Logic_Vector(9 DOWNTO 0) b : OUT Std_Logic_Vector(3 DOWNTO 0);END encoder;ARCHITECTURE beh_encoder OF encoder ISBEGIN WITH a SELECT b= “0110” WHEN “0111111111”, “0111” WHEN “1011111111”, “1000” WHEN “1101111111”, “1001” WHEN “1110111111”, “1010” WHEN “1111011111”, “1011” WHEN “1111101111”, “1100” WHEN “1111110111”, “1101” WHEN “1111111011”, “1110” WHEN “1111111101”, “1111” WHEN “1111111110”, “0000” WHEN OTHERS;END beh_encoder;补充：优先编码器LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY encoder ISPORT(a : IN Std_Logic_Vector(9 DOWNTO 0) b : OUT Std_Logic_Vector(3 DOWNTO 0);END encoder;ARCHITECTURE beh_encoder OF encoder ISBEGIN WITH a SELECT b= “0110” WHEN “0XXXXXXXXX”, “0111” WHEN “10XXXXXXXX”, “1000” WHEN “110XXXXXXX”, “1001” WHEN “1110XXXXXX”, “1010” WHEN “11110XXXXX”, “1011” WHEN “111110XXXX”, “1100” WHEN “1111110XXX”, “1101” WHEN “11111110XX”, “1110” WHEN “111111110X”, “1111” WHEN “1111111110”, “0000” WHEN OTHERS;END beh_encoder;(2).时钟RS触发器。LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY clk_rs_ff IS PORT(r,s,cp:IN Std_Logic; q,nq : BUFFER Std_Logic);END clk_rs_ff ;ARCHITECTURE beh_clkrsff OF clk_rs_ff ISBEGIN ASSERT NOT(r=1 AND s=1) REPORTControl error SEVERITY Error; PROCESS(r,s,cp) BEGIN IF cp=1 THEN q= s OR (NOT r AND q); nq= NOT( s OR (NOT r AND q); END IF; END PROCESS;END beh_clkrsff;(3).带复位端、置位端、延迟为15ns的响应CP下降沿的JK触发器。LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY jk_ff IS GENERIC (tpd:Time:=15 ns); FORT (r,s,j,k,cp:IN Std_Logic; q,nq:BUFFEER Std_Logic);END jk_ff;ARCHITECTURE beh_jkff OF jk_ff ISBEGIN ASSERT NOT(r=0 AND s=0) REPORT Control error SEVERITY Error; PROCESS(r,s,cp) BEGIN IF r=0 THEN q=0 AFTER tpd; nq=1 AFTER tpd; ELSIF s=0 THEN q=1 AFTER tpd; nq=0 AFTER tpd; ELSIF (cpEvent AND cp=0) THEN q=j AND nq OR NOT k AND q AFTER tpd; nq=NOT( j AND nq OR NOT k AND q) AFTER tpd; END IF; END PROCESS;END beh_jkff;(4).集成计数器74161。LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;USE IEEE.Std_Logic_Unsigned.ALL; ENTITY counter16 IS PORT (cr, ld, cp, ctt, ctp : IN Std_Logic; d : IN Std_Logic_Vector(3 DOWNTO 0); q : BUFFER Std_Logic_Vector(3 DOWNTO 0); co :OUT Bit);END counter16;ARCHITECTURE behav_ctr16 OF counter16 ISBEGIN PROCESS (cr,cp) BEGIN IF cr=0 THEN q=“0000”; ELSIF (cpEvent AND cp=1) THEN IF ld=0 THEN q=d; ELSIF (ctt=1 AND ctp=1) THEN IF q=“1111” THEN q=“0000”; ELSE q=q+“0001”; END IF; END IF; END IF; END PROCESS; co=1 WHEN (q=“1111” AND ctt=1) ELSE 0;END beh_ctr16;(5).集成移位寄存器74194。 LIBRARY IEEE; USE IEEE.Std_Logic_1164.ALL; ENTITY srg IS PORT(cr, cp : IN Std_Logic; d : IN Std_Logic_Vector(3 DOWNTO 0); sl, sr: IN Std_Logic; m: IN Std_Logic_Vector(1 DOWNTO 0); q: BUFFER Std_Logic_Vector(3 DOWNTO 0); END srg; ARCHITECTURE behav_srg OF srg IS BEGIN PROCESS(cr, cp) BEGIN IF cr=0 THEN q q q qNULL; -空操作，即保持 END CASE; END IF; END PROCESS; END behav_srg;3.6、(2).由D触发器构成的异步二进制模8计数器异步2k进制计数器的电路结构计数规律触发方式上升沿下降沿加法减法LIBRARY IEEE;USE IEEE.Std_Logic_1164.ALL;ENTITY asyn_ctr8 IS PORT(cp : IN Bit; q : BUFFER Std_Logic_Vector( 2DOWNTO 0);END ctr8;ARCHITECTURE struct_ctr8 OF asyn_ctr8 IS COMPONENT d_ff PORT (clk,d : IN Std_Logic; q,nq :OUT Std_Logic); END COMPONENT; SIGNAL nq0,nq1,nq2 : Std_Logic;BE