[工学]北大数字集成电路课件--22_Verilog的编写风格.ppt

第22章 Coding Styles for Synthesis,if语句和case语句的编码风格 if语句和case语句中晚到达信号的处理 逻辑块的编码风格 高性能编码技术 其它问题,主要内容：,if 语句,module single_if(a, b, c, d, sel, z); input a, b, c, d; input 3:0 sel; output z; reg z; always (a or b or c or d or sel) begin if (sel3) z = d; else if (sel2) z = c; else if (sel1) z = b; else if (sel0) z = a; else z = 0; end endmodule,module mult_if(a, b, c, d, sel, z); input a, b, c, d; input 3:0 sel; output z; reg z; always (a or b or c or d or sel) begin z = 0; if (sel0) z = a; if (sel1) z = b; if (sel2) z = c; if (sel3) z = d; end endmodule,例1.1a 单个 if 语句,例1.1b 多重 if 语句,注意代码的优先级,if语句,case语句,module case1(a, b, c, d, sel, z); input a, b, c, d; input 3:0 sel; output z; reg z; always (a or b or c or d or sel) begin casex (sel) 4b1xxx: z = d; 4bx1xx: z = c; 4bxx1x: z = b; 4bxxx1: z = a; default: z = 1b0; endcase end endmodule,casex具有使用无关项的优点，不用列出sel的所有组合。,例1.2 case 语句,晚到达信号处理,设计时通常知道哪一个 信号到达的时间要晚一些。这些信息可用于构造HDL，使到达晚的信号离输出近一些。 下面的例子中，针对晚到达信号重新构造if和case语句，以提高逻辑性能。,晚到达的是数据信号,顺序if语句可以根据关键信号构造HDL。在例1.1a 中，输入信号d处于选择链的最后一级，也就是说d最靠近输出。 假如信号b_is_late是晚到达信号，我们就要重新构造例1.1a使其最优化。,具有优先级的if结构,module single_if(a, b, c, d, sel, z); input a, b, c, d; input 3:0 sel; output z; reg z; always (a or b or c or d or sel) begin if (sel1) z = b_is_late; else if (sel2) z = c; else if (sel3) z = d; else if (sel0) z = a; else z = 0; end endmodule,无优先级的if结构,晚到达的是数据信号,晚到达的是控制信号,如果晚到达信号作为if语句条件分支的条件，也应使这个信号离输出最近。在下面的例子中，CTRL_is _late是晚到达的控制信号,module single_if_late(A, C, CTRL_is_late, Z); input 6:1 A; input 5:1 C; input CTRL_is_late; output Z; reg Z; always (C or A or CTRL_is_late) if (C1 = 1b1) Z = A1; else if (C2 = 1b0) Z = A2; else if (C3 = 1b1) Z = A3; else if (C4 = 1b1 endmodule,晚到达的是控制信号,module single_if_late(A, C, CTRL_is_late, Z); input 6:1 A; input 5:1 C; input CTRL_is_late; output Z; reg Z; always (C or A or CTRL_is_late) / late arriving signal in if condition if (C4 = 1b1 endmodule,if-case嵌套语句,module case_in_if_01(A, DATA_is_late_arriving, C, sel, Z); input 8:1 A; input DATA_is_late_arriving; input 2:0 sel; input 5:1 C; output Z; reg Z; always (sel or C or A or DATA_is_late_arriving) if (C1) Z = A5; else if (C2 = = 1b0) Z = A4; else if (C3) Z = A1; else if (C4) case (sel) 3b010: Z = A8; 3b011: Z = DATA_is_late_arriving; 3b101: Z = A7; 3b110: Z = A6; default: Z = A2; endcase else if (C5 = = 1b0) Z = A2; else Z = A3; endmodule,if-case嵌套语句,Case语句,if语句,if-case嵌套语句修改后,always (sel or C or A or DATA_is_late_arriving) begin if (C1) Z1 = A5; else if (C2 = 1b0) Z1= A4; else if (C3) Z1 = A1; else if (C4) case (sel) 3b010: Z1 = A8; /3b011: Z1 = DATA_is_late_arriving; 3b101: Z1 = A7; 3b110: Z1 = A6; default: Z1 = A2; endcase else if (C5 = 1b0) Z1 = A2; else Z1 = A3; FIRST_IF = (C1 = 1b1) | (C2 = 1b0) | (C3 = 1b1); if (!FIRST_IF end,if-case嵌套语句修改后,逻辑构造块的编码格式,下面介绍某些常用逻辑块，如译码器的不同的编码格式。每种块给出了一个通常格式和建议格式。 所有的例子的位宽都是参数化的。,3-8译码器,index方式,loop方式,译码器,优先级编码器高位优先,1?_? : 111 01?_? : 110 001?_? : 101 0001_? : 100 0000_1? : 011 0000_01? : 010 0000_001? : 001 0000_000? : 000,优先级编码器,线性结构,树形结构,归约XOR,module XOR_reduce (data_in, data_out); parameter N = 5; input N-1:0 data_in; output data_out; reg data_out; function XOR_reduce_func; input N-1:0 data; integer I; begin XOR_reduce_func = 0; for (I = N-1; I = 0; I=I-1) XOR_reduce_func = XOR_reduce_func dataI; end endfunction always (data_in) data_out = XOR_reduce_func(data_in); endmodule,线性结构,归约XOR,线性结构,树形结构,归约XOR,module XOR_tree(data_in, data_out); parameter N = 5; parameter logN = 3; input N-1:0 data_in; output data_out; reg data_out; function even; input 31:0 num; even = num0; endfunction function XOR_tree_func; input N-1:0 data; integer I, J, K, NUM; reg N-1:0 temp, result; begin tempN-1:0 = data_inN-1:0; NUM = N; for (K=logN-1; K=0; K=K-1) begin J = (NUM+1)/2; J = J-1;,if (even(NUM) for (I=NUM-1; I=0; I=I-2) begin resultJ = tempI tempI-1; J = J-1; end else begin for (I=NUM-1; I=1; I=I-2) begin resultJ = tempI tempI-1; J = J-1; end result0 = temp0; end tempN-1:0 = resultN-1:0; NUM = (NUM+1)/2; end XOR_tree_func = result0; end endfunction always (data_in) data_out = XOR_tree_func(data_in); endendmodule,树形结构,高性能编码技术,在某些情况下，可以通过重复逻辑来提高速度。 在下面的例子中，CONTROL是一个晚到达的输入信号。要提高性能，就要减少CONTROL到输出之间的逻辑。,module BEFORE (ADDRESS, PTR1, PTR2, B, CONTROL, COUNT); input 7:0 PTR1,PTR2; input 15:0 ADDRESS, B; input CONTROL; / CONTROL is late arriving output 15:0 COUNT; parameter 7:0 BASE = 8b10000000; wire 7:0 PTR, OFFSET; wire 15:0 ADDR; assign PTR = (CONTROL = 1b1) ? PTR1 : PTR2; assign OFFSET = BASE - PTR; assign ADDR = ADDRESS - 8h00, OFFSET; assign COUNT = ADDR + B; endmodule,高性能编码技术,高性能编码技术,module PRECOMPUTED (ADDRESS, PTR1, PTR2, B, CONTROL, COUNT); input 7:0 PTR1, PTR2; input 15:0 ADDRESS, B; input CONTROL; output 15:0 COUNT; parameter 7:0 BASE = 8b10000000; wire 7:0 OFFSET1,OFFSET2; wire 15:0 ADDR1,ADDR2,COUNT1,COUNT2; assign OFFSET1 = BASE - PTR1; / Could be f(BASE,PTR) assign OFFSET2 = BASE - PTR2; / Could be f(BASE,PTR) assign ADDR1 = ADDRESS - 8h00 , OFFSET1; assign ADDR2 = ADDRESS - 8h00 , OFFSET2; assign COUNT1 = ADDR1 + B; assign COUNT2 = ADDR2 + B; assign COUNT = (CONTROL = 1b1) ? COUNT1 : COUNT2; endmodule,高性能编码技术,在下面的例子中，if语句的条件表达中包含有操作符。,module cond_oper(A, B, C, D, Z); parameter N = 8; input N-1:0 A, B, C, D; /A is late arriving output N-1:0 Z; reg N-1:0 Z; always (A or B or C or D) begin if (A + B 24) Z = C; else Z = D; end endmodule,高性能编码技术,若条件表达式中的信号A是晚到达信号。因此要移动信号A使其离输出近一些。,高性能编码技术,module cond_oper_improved (A, B, C, D, Z); parameter N = 8; input N-1:0 A, B, C, D; / A is late arriving output N-1:0 Z; reg N-1:0 Z; always (A or B or C or D) begin if (A 24 - B) Z = C; else Z = D; end endmodule,其它要注意的问题,不要引入不必要的latch 敏感表要完整 非结构化的for循环 资源共享,不要产生不需要的latch,条件分支不完全的条件语句（if和case语句）将会产生锁存器,always (cond_1) begin if (cond_1) data_out = data_in; end,always (sel or a or b or c or d) begin case (sel) 2b00: a = b;