CadenceAllegroSI培训课件L.ppt

1,Lesson 2 Allegro PCB SI Design Flow: Pre-Placement,Identify board database setup requirements. Use the Database Setup Advisor to set up a board database. Use the Signal Analysis Library Browser. Translate IBIS (.ibs) signal models into Cadence Device Model Library (.dml) format.,2,The Allegro PCB SI Design Flow,Pre-Placement Solution Space Analysis Constraint-Driven Floorplanning Constraint-Driven Routing Post-Route DRC Post-Route Analysis,The Allegro PCB SI Design Flow consists of the following six steps:,E,You are Here,Double Click Here to Open the Image,3,Design Flow: Pre-Placement,Standard form factors, mechanical restrictions, and standard practices often predefine locations of critical components. Electrical design must start with these requirements, or present a strong case why things should be changed. Pre-placed design is usually created by the CAD group as a starting point for design.,Chip set placement predetermined,4,Board Setup Requirements,Allegro PCB SI needs several items in place to correctly extract and apply topology templates. These items are:,A netlist A board file with a defined layout cross-section Identification of DC nets & assignment of their DC VALUE property Properly assigned CLASS properties on the components Simulation models for the components associated with the topology Properly assigned properties on the pins of components,5,Database Setup Advisor,The first screen of the Database Seup Advisor. Explains the use of Database Setup Advisor. Describes the steps you must take to set up the database correctly. “Set up Right, Set up Once”.,Click Next to proceed to the next step in the process to complete the Database Setup.,6,Database Setup Advisor: Cross-section,Explains the use of layout cross-section in the simulation. Describes the steps to edit layout cross-section.,Click here to open the Layout Cross-section Editor,7,What is the Layout Cross-Section?,The layout cross section defines the physical and electrical characteristics of the printed circuit board.,Board cross section defines conductor and dielectric (insulator) layers. Determines overall board thickness. Trace width and board cross-section determine trace characteristics. Distance between traces and reference planes has primary effect on: Impedance: increases with distance Crosstalk: increases with distance,8,Defining the Layout Cross-Section,From the Allegro PCB SI menu select Setup Cross-Section. Layout Cross-Section editor consists of ordered layers of your board.,Activate Differential Mode Layout Cross Section Editor,9,Materials Editor,Type the command “define materials” at the Command prompt of the tool command console to invoke Materials Editor. From Allegro PCB SI menu select Setup Materials.,10,DC Voltages,Allegro PCB SI needs source voltages for terminators and capacitors to build an electrically correct circuit.,Terminated buses to 1.5 Volts,11,Database Setup advisor: DC Nets,From the Allegro PCB SI menu select: Tools Setup Advisor.,Describes the steps to identify the DC Nets.,Click to select the Net from the list,Voltage level currently assigned to the selected Net,You can also invoke the Identify DC Nets form from the Allegro PCB SI menu by selecting: Logic Identify DC Nets.,Uses,12,Device CLASS and PINUSE Properties,ICs (Active) Resistors, Inductors, Capacitors (Passive) Connectors,IC DISCRETE IO,INPUT, OUTPUT, BI, TRISTATE, POWER, GROUND, OCA, OCL, NC UNSPEC UNSPEC,IBIS (may include Macromodels) - dml ESpice -dml Spice subckts and RLGC matrix formats with dml wrappers - dml,Component Type,CLASS,PINUSE,Signal Model Type,PCB SI needs this model to trace Xnet connectivity. Extraction and analysis will fail otherwise.,PCB SI uses this to determine buffer type for SigXplorer and SigNoise simulations.,PINUSE must match between topology template and design when templates are applied (depending on the mapping strategy used).,May be used to model parasitics between boards,Notes,13,Database Setup Advisor: Device Setup,From the Allegro PCB SI menu select: Tools Setup Advisor.,14,Editing the Parts List,From the Allegro PCB SI menu select: Logic Parts List.,Current Parts List,Choose the parts from these libraries.,Class assignment for the components.,Assign / Modify component information,15,Editing Pin Types,From the Allegro PCB SI menu select: Logic Pin Type.,Components or Net Listings,Selected Component Pins,Available Pin Types,16,Lab: Board Setup Requirements Session 1 Run the Database Setup Advisor Edit Layout Cross-section Identify DC Nets Correct CLASS and PINUSE properties assigned to the components,Lab,The Board Setup Requirement lab will be continued in the next lab session.,17,Database Setup advisor SI Models,Signal Model,18,Signal Model Assignment Form,From the Allegro PCB SI menu select: Analyze SI/EMI Sim Model.,Assigned Models,Model library location,Invokes appropriate editor to modify the selected model,Displays the SigNoise Preference,Displays the Model Browser,Displays the correct Create Model form for the model selected,List of the board components,19,Auto setup of Models,From the Allegro PCB SI menu select: Analyze SI/EMI Sim Model.,The Signal Models located in the library are associated to the devices,New models created are stored in Working Device Library,Auto Setup Components,20,Signal Analysis Library Browser,From the SigXplorer-PCB SI menu select: Analyze Libraries or from Allegro PCB SI menu select: Analyze SI/EMI Sim Library.,Current working libraries,Device Libraries section,Interconnect libraries section,=,21,Translating and Adding Libraries,An Index file (.ndx) is a group of library files that have been merged and indexed together. You can use the models for simulation, but cannot modify the index file in any way.,You can translate these types of signal models to Cadence Device Model format.,22,The Model Browser,List of model types you can clone or create.,23,Model Integrity,Select: Start Programs Allegro SPB 15.5 Model Integrity,gutter,24,Model Integrity Features,Platform to translate, validate, edit and create models. Convert SPICE models to IBIS models Convert IBIS, Touchstone and QUAD models into SigNoise models Edit IBIS and SigNoise models Validate the models Convert Cadence SPICE (ESpice) models to generic SPICE/HSpice models (use spc2spc utility) Convert EBD models to SigNoise (dml) models. Create dml wrapper for HSpice models to obtain BlackBoxModel and MacroModels that can be used in Allegro PCB SI tool suite. Easy to identify, locate and rectify errors and warnings in the mode