Keysight_DisplayPort 1.3 的物理层测挑战与测试方案.pdf

Page 4-Jan-16 Phy Layer Test Requirements for DisplayPort1.3 Li Jun Digital Application Engineer Webinar Jan 6th, 2016 Page 4-Jan-16 Keysight Standards Program General Introduction to DisplayPort New Forces Present Testing DisplayPort Devices Future Issues Final Words DisplayPort 1.3 Phy Topics Today 2 Page 4-Jan-16 Keysight Standards Program General Introduction to DisplayPort New Forces Present Testing DisplayPort Devices Future Issues Final Words DisplayPort 1.3 Phy Topics Today 3 Page 4-Jan-16 DisplayPort 1.3 Phy Keysight Digital Standards Program Our solutions are driven and supported by Keysight experts involved in international standards committees: Joint Electronic Devices Engineering Council (JEDEC) PCI Special Interest Group (PCI-SIG) Video Electronics Standards Association (VESA) Serial ATA International Organization (SATA-IO) USB-Implementers Forum (USB-IF) Mobile Industry Processor Interface (MIPI) Alliance And many others Were active in standards meetings, workshops, plugfests, and seminars We get involved so you benefit with the right solutions when you need them 4 Page 4-Jan-16 DisplayPort 1.3 Phy Memory Perry Keller Board of Directors JEDEC Compliance Chair UFSA Computer Rick Eads Board of Directors PCI-SIG Optical Greg LeCheminant Contributor IEEE, OIF- CEI, T11 FC HDMI Stefan Friebe Contributor HDMI Storage Matthew Woerner Contributor SATA-IO, T10 SAS DisplayPort Brian Fetz Board of Directors VESA Contributor VESA Phy Sub Group USB-IF Compliance MIPI Roland Scherzinger TSG Member UniPro Vice Chair MIPI Alliance LPDDR4, UFS PCIe G3, G4 PAM-4, CEI 3.1 HDMI 2.0 SAS-3 DP 1.3 USB Type C D/M/CPHY, UniPro We understand your future requirements, because we help shape them. USB Jit Lim Contributor USB-IF USB 2.0,3.0,3.1 5 Page 4-Jan-16 Keysight Standards Program General Introduction to DisplayPort New Forces Present Testing DisplayPort Devices Future Issues Final Words DisplayPort 1.3 Phy Topics Today 6 Page 4-Jan-16 DisplayPort 1.3 Phy Review of DisplayPort The DisplayPort standard is administered by VESA1. Introduced in 2007. Graphics interface from GPU to Display through external cable. DP technology addresses embedded models as well. Up to 4 forward differential lanes with fixed data rates. ANSI 8b/10b encoded. Can daisy chain up to 32 monitors. Two established DisplayPort connectors. 1. Video Electronics Standards Association 7 Page 4-Jan-16 DisplayPort 1.3 Phy Review of DisplayPort Interface EDID Tx Driver Logic Decode Main Link AUX Hot Plug Detect DisplayPort Sink Interrupt 4 Differential Lanes DisplayPort Source 1 Differential Lane Main Link Up to 4 differential lanes: 3 possible bit rates TX: 4 possible level settings 4 possible pre-emphasis settings Spread Spectrum Clocking (optional) Dual Mode optional RX: Receiver individual clock recovery Receiver Tolerance curve specified. Receiver Sensitivity = 50mV Ck Data Data Level PE Bit Recovery DPCD AUX Channel Phy Layer Bit rate at 1Mbs Manchester II encoded Purpose Link Management Test Mode control 8 Page 4-Jan-16 DisplayPort 1.3 Phy DP: Source and Sink communication over AUX Source sees connection: HPD high = sink/cable connected Source then reads the EDID data: Know preferred capability Source then reads DPCD (00h-FFh): Know DP capabilities Source will set up highest bit rate, lowest level on lanes and starts link training process. Sink updates link status on DPCD registers. Source reads DPCD values evaluates results to either progress through training, change level, pre-emphasis or bit rate HPD used for link connection as well as for link service. Connection: 9 Page 4-Jan-16 DisplayPort 1.3 Phy Total useable data transfer rate for DP 1.3 = 25.92 Gbps Using the DisplayPort Multi-Stream feature, HBR3 can enable the following example display configurations, without the use of compression: Two 4K UHD (3840 x 2160) displays Up to Four 2560 x 1600 displays Up to Seven 1080p or 1920 x 1200 displays One 4K UHD display with up to Two 2560 x 1600 displays 10 DP: DisplayPort 1.3 Coming Page 4-Jan-16 Keysight Standards Program General Introduction to DisplayPort New Forces Present Testing DisplayPort Devices Future Issues Final Words DisplayPort 1.3 Phy Topics Today 11 Page 4-Jan-16 DisplayPort 1.3 Phy New Forces Present New DisplayPort1.3 Specification USB Type C Connector USB3.1 Alternate Mode Specifications Power Delivery Compliance Program Direction New Data Rate, new Reference Equalizer Joint Standard for validation Target connector for portables and beyond Not only new requirements for power but back channel communication DP, MHL, Thunderbolt Interoperability program rigor 7/26 8/11 9/17 9/22 03/15 2014 11/17 Today USB3.1 ECNs DP1.3 DP Alt Mode USB Power Delivery 2.0 USB Type C connector 2015 MHL Alt Mode TBT Alt Mode VESA Compliance Mgr 12 Page 4-Jan-16 DisplayPort 1.3 Phy New Forces Present New DisplayPort1.3 Specification: Phy Layer Implications DP TX RBR, HBR, HBR2, HBR3 De- Embed Fixture A c q Embed Cable Model CTLE DFE Mathematical Processing Measurement Eye Diagram Jitter Measurements Add Channel Loss Level Control, Jitter Addition Crosstalk Addition DP RX RBR, HBR, HBR2, HBR3 Calibration Test DP TX Testing DP RX Testing 13 Page 4-Jan-16 DisplayPort 1.3 Phy New Forces Present Management of a power network and device modes through a one line communication channel Devices in a link can dynamically re-assign USB Type C pin functionality. Universally accepted interface going to 10Gbs and beyond. A Low Profile, orientation independent, high data rate connection (40Gbs). 14 Page 4-Jan-16 Keysight Standards Program General Introduction to DisplayPort New Forces Present Testing DisplayPort Devices Future Issues Final Words DisplayPort 1.3 Phy Topics Today 15 Page 4-Jan-16 DisplayPort 1.3 Phy DP Transmitter Testing: Whole Channel Eye Cable Loss Model CTLE DFE (50mv max) Tx Driver Logic Decode DisplayPort Source Ck Data Level PE TP2 TP3 TP3EQ Math performed on oscilloscope on TP2 acquisition DUT Sink REFERENCE EQUALIZER Standard DP mDP USB Type C 16 Cable Model Page 4-Jan-16 DisplayPort 1.3 Phy Test RBR HBR HBR2 HBR3 3-1 Eye Diagram PRBS7 PRBS7/ HBR2CPAT HBR2CPAT TP3EQ Arbitrary TP3EQ 3-2 Non PreEmphasis Level PRBS7 PRBS7 PRBS7 Arbitrary 3-3 Pre-Emphasis Level PRBS7 PRBS7 PLTPAT Arbitrary 3-4 Inter Pair Skew D10.2 D10.2 D10.2 Arbitrary 3-11 Non ISI Jitter PRBS7 PRBS7 NA NA 3-11 Deterministic Jitter NA NA/ HBR2CPAT HBR2CPAT TP3EQ Arbitrary TP3EQ 3-12 Total Jitter PRBS7 PRBS7/ HBR2CPAT/D10.2 CP2520/D10.2 TP3EQ Arbitrary TP3EQ 3-14 Main Link Frequency D10.2 D10.2 D10.2 Arbitrary 3-15 Spread Spectrum Modulation Frequency D10.2 D10.2 D10.2 Arbitrary 3-16 Spread Spectrum Deviation Accuracy D10.2 D10.2 D10.2 Arbitrary 3-18 Dual Mode TMDS Clock All appropriate Data Rates/Random Pattern 3-19 Dual Mode TMDS Eye Test All appropriate Data Rates/Random Pattern DisplayPort Tests: Patterns and Test Point All connections are TP2 unless noted 17 Page 4-Jan-16 DisplayPort 1.3 Phy Test Levels Pre-Emphasis 3-1 Eye Diagram RBR/HBR: Setting 2 HBR2/3: User Choice RBR/HBR: Setting 0 HBR2/3: User Choice 3-2 Non PreEmphasis Level All Settings Setting 0 3-3 Pre-Emphasis Level All Settings All Valid Settings 3-4 Inter Pair Skew Setting 2 Setting 0 3-11 Non ISI Jitter RBR/HBR: All settings RBR/HBR: Setting 0 3-11 Deterministic Jitter RBR/HBR: All settings HBR2/3: User Choice RBR/HBR: Setting 0 HBR2/3: User Choice 3-12 Total Jitter RBR/HBR: All settings HBR2/3: User Choice RBR/HBR: Setting 0 HBR2/3: User Choice 3-14 Main Link Frequency Setting 2 Setting 0 3-15 SSC Modulation Frequency Setting 2 Setting 0 3-16 SSC Deviation Accuracy Setting 2 Setting 0 3-18 Dual Mode TMDS Clock No choice 3-19 Dual Mode TMDS Eye Test No choice DisplayPort Tests and Levels & Pre-Emphasis 18 Page 4-Jan-16 DisplayPort 1.3 Phy Know that there are many test conditions! Eye Diagram: One Level, One P-E setting, 2 SSC states, 4 Lanes, 4 bit rates, two cable conditions for HBR2/3: 2*4*4 +8+8 = 48 Eye Diagrams! Pre-Emphasis Tests: 10 combinations between Level and Pre-Emphasis, 4 bit rates, 2 SSC states, 4 lanes = 320 Tested states! The details of test are handled by compliance test application test plan capability DP1.3 incremental: 16 tests DP1.3 incremental: 80 tests 19 Page 4-Jan-16 DisplayPort 1.3 Phy Test Software Facilitation Device Definition to Run Test Device Definition Test Connection Test Selection 20 Page 4-Jan-16 DisplayPort 1.3 Phy Automation considerations In order to test without manually setting the many conditions, a means to control bit rate, pre emphasis, and level is required. Need a device that acts like a sink but is very controllable. This is called a Reference Sink. Tx Driver Logic Decode DisplayPort Source Ck Data Level PE Reference Sink AUX HPD DPR100 The test application communicates with DPR100 to set DUT to correct state according to the test plan DP1.3 testing requirements may NOT use TEST MODE but use an abbreviated link training process to control level, bit rate, and pre-emphasis. 21 Page 4-Jan-16 DisplayPort 1.3 Phy DisplayPort RX Testing Table 4.4 from DisplayPort CTS 1.2b Sink Jitter Tolerance which provides a stressed signal of known pattern to the DUT and the DUT measures the number of bit errors. Sink Jitter Tolerance is performed ONE LANE at a time. The Stressed Signal: A maximum Eye Height is specified A maximum Eye Width is specified These conditions are achieved with a cocktail of jitter (RJ, SJ, ISI), Crosstalk or injected signal, and level control and the process is detailed in the Compliance Test Specification. 22 Page 4-Jan-16 DisplayPort 1.3 Phy Sink Testing CDR Bit Error Expected Patterns CkDR Freq Lock Symbol Lock EQ Display DPCD Reg EDID Main Link AUX Hot Plug Detect DisplayPort Sink Interrupt Lane Under Test 1 Differential Lane Data Bit Recovery DPCD Reference Source Pattern Generator # Bit Errors Test Pattern DisplayPort Sink 23 Page 4-Jan-16 Keysight Standards Program General Introduction to DisplayPort New Forces Present Testing DisplayPort Devices Future Issues Final Words DisplayPort 1.3 Phy Topics Today 24 Page 4-Jan-16 DisplayPort 1.3 Phy Future Issue USB3.1 Orientation Independence Doubles the number of Ports to test! Right now this issue is not specifically addressed in the Compliance Test considerations, but is generally acknowledged that the second port must be validated as well. DP1.3 Alternate Modes Increases the number of compliance regimens to run! The attractiveness of the USB Type C connector has resulted in a number of other standards that have targeted it. Each of these standards have their own testing requirements. 25 Page 4-Jan-16 DisplayPort 1.3 Phy Future Issue Power Management Device can Sink and/or Source Current Right now this issue is not specifically addressed in the CTS for the High Speed link, but it is entirely possible that all notable modes of operation will have to be active for compliance testing. Further, will there be a number of loading/charging conditions required, or just worst case? Regardless of the compliance requirement, validation engineers will test in a great many conditions Device can operate certain devices over VConn. This could be considered another operational state. Testing under load conditions for VConn: a number of established load conditions or just worst case? VConn Power Management 26 Page 4-Jan-16 DisplayPort 1.3 Phy 27 USB Channel Models SCD1, SCD2, Ping DP Channel Model TX1 RX1 Downstream Facing Port TX2 RX2 Mux Cc Line Orientatin Vconn, Connection Vbus Type C TX RX PING LFPS Toggles CMM SigTest C New TPA BW=20GHz Switch Matrix Integration: Multiple protocols, Power Control, Switching, Fixturing, Automation, Channels 27 Future Issue Page 4-Jan-16 DisplayPort 1.3 Phy Test System Changes Test Signal Breakout Power Delivery Controller Power Supply Switch Matrix (Optional) Pattern Generator, BERT Oscilloscope Type C connector Application Software RX Test Application Software TX Test 28 N7015A Page 4-Jan-16 DisplayPort 1.3 Phy Future Issues Test Time Reduction Arbitrary Data vs Test Mode New Test methods Variation in test vendor algorithms Test Coverage simplifications Worst Case Test Highest probability of Interoperability issues. Coverage Correlation Test plan control/flow for Unattended testing 29 Page 4-Jan-16 Source Test Solution V series nfiniium Real Time Oscilloscopes U7232D DisplayPort Compliance Test SW Computer Motherboa