[信息与通信]TFTLCD驱动原理与系统.ppt

tft lcd 驅動原理與系統,tft lcd 驅動原理與系統,液晶及液晶顯示器簡介 tft lcd 驅動原理 影響tft lcd 畫面品質的因素 tft lcd driver ic lcd 數位界面簡介 背光板簡介 未來趨勢與走向,被動式/主動矩陣式液晶顯示器passive/active matrix lcd,y electrode,x electrode,pixel,the color pixel of tft lcd,color filter substrate,tft substrate,white light,color light,r,g,b,b,g,r,clc,clc,clc,arrangement of color filter,stripe,triangle,mosaic,aperture ratio,a-si,drain electrode,gate electrode,insulator,source electrode,n+ a-si,adjacent gate electrode,insulator (dielectric substance),display electrodes,tft pixel,effective area: 40.7%,capacitor,tft lcd 驅動,基本驅動波形 極性反轉(polarity inversion) - frame, row, column, dot 電容耦合驅動 - 二階,三階,四階,timing chart of tft lcds,frame time,time,gate,1 2 3 n,1h,tftl lcds driving method,frame n columns,frame n+1 columns,frame n columns,frame n+1 columns,column inversion,dot inversion,frame n columns,frame n+1 columns,frame n columns,frame n+1 columns,frame inversion,row inversion,direct driving of tft lcds,dc bias of common,1 frame / 1 line,garyscal voltage,v63 v62 . . . . . . . . v1 v0,v0 v1 . . . . . . . . v62 v63,vcom ac modulation addressing of tft lcds,1 frame / 1 line,common waveform,graylevel voltage,v0,v0,v1,v1,v2,v2,v63,v62,v62,v63,direct driving vs vcom modulation,direct driving frame , row , column & pixel inversion available cancel crosstalk & remove flicker ：image quality improve power dissipation vcom modulation available frame & row inversion poor power dissipation,影響 lcd 畫面品質的因素,horizontal crosstalk vertical crosstalk shading crosstalk,液晶電容的效應,液晶電容clc會隨液晶作用電壓的改變而變化，因此在驅動液晶時會有殘存的dc成份，其所造成的影響 image sticking. picture flicker. 液晶作用電壓大時，液晶分子趨向平行電場方向排列 液晶作用電場小時，液晶分子趨向垂直電場方向排列, vp = vgd vgd ,cgd vghl,cgd + cs + c,cgd vghl,cgd + cs + c,horizontal line crosstalk,r,g,b,csc,csc,csc,color filter substrate,b,a,signal of a line,signal of b line,common waveform,difference of effective voltage in b line,black level,gray level,gray level,horizontal area crosstalk,b,a,signal of a line,signal of b line,common waveform v1 v2,v1,v2,difference of effective voltage in b line,tft lcd driver ic,scan (gate, row) driver data (source, column) driver high voltage, mixed mode usually tcp package vendors：ti japan, sharp, nec, toshiba, matsushita, hitachi, samsung, lg, vivid, winbond (cirrus logic, vivid), mosel(sharp) maybe in the future, driver ic is not necessary in large size lcd,the block diagram of the tft lcd module,tft-lcd panel,ccfl backlight,data driver,scan driver,timing controller,rgb,clk hsx vsx,tft lcd module,video signal timing spec.,a,d,e,c,b,horizontal display area,hs,total,display area,o,p,q,r,s,vertical display area,vs,tft-lcd module,controller,no.1,no.4,256,256,color tft-lcd panel 1280 x 3x 1024,r,g,b,no.1,no.9,no.10,384,384,384,control signals (cpv,di01,v1,v2),gma0gma9,control signals(clk,ei01),display data 36(6bits x 3x2),video signal timing spec.,resolution vs outputs - 1,gate driver no. of drivers and no.of output channels,channels：120, 120/128, 150/154, 192/200, 240, 256,resolution vs outputs - 2,source driver no. of drivers and no.of output channels,channels：192/240, 300/309, 384, 384/402,resolution vs fmax,解析度愈高，充電時間更短，driver ic的fmax也要愈快,data driver key specifications,channel number gray scale (6bits, 8bit ) max operation freq. (45mhz, 55mhz,65mhz ) pixel charging time (eg. r=2k,c=20pf,6.5 s90%, 11.5 s 100%) line or column/dot inversion output voltage deviation (10mv,5mv,3mv) operation voltage digital：5v, 3.3v, 2.5v analog：10v 15v others(data inversion, low-power mode, offset canceling, rsds/lvds inputetc),driver ic trend,240,300/309,384/402, 480,65um,40um,50um,4055mhz,65mhz,85mhz,3v/5v,10v/15v,3v/5v/10v,line inversion,dot inversion,line/dot inversion,6 bit(64 gray scale),8 bit(256 gray scale),2 level gate driver,3 level gate driver,94 95 96 97 98 98 2000,uxga 1600 x 1200,sxga 1280 x 1024,xga 1024 x768,svga 800 x 600,vga 640 x 480,display resolution trend,gray scale gray scale driving method output voltage operation frequency tcp ilb pitch output channel,gate,data driver ic spec,lcd數位界面簡介,類比pc界面簡介 lcd數位界面簡介 lvds tmds gvif,analog interface & tft lcd module,graphics controller,osd,adc,buffer,controller,pll,analog rgb,hs vs,digital rgb,hs vs,clk hsx vsx,timing controller,scan driver,tft-lcd panel,digital data driver,ccfl backlight,pc acd module tftlcd module,digital interface & tft lcd module,lvds/ panellink rx,digital rgb,clock hs vs,timing controller,scan driver,tft-lcd panel,digital data driver,ccfl backlight,graphics controller,lvds/ panellink tx,digital rgb,clock hs vs,pc,cable,tft-lcd module,digital interface,high image quality long transmission distance simple hardware high speed, emi problem adc/dac not needed transmitter/receiver needed main technology lvds, tmds, gvif standard openldi, dfp, dvi, dism,the digital interface -lvds,lvds interface (ti, ns, thine) low voltage differential signaling mainstream in the notebook pc now(close system) 7x internal clock pll range：vga(20mhz)to xga (65mhz) low voltage swings (0.250mv 0.345mv 0.450mv) reducing emi & high edge sharpness image number of cable line：4 , 5 , 9 pairs long distance transmission( 5m ),lvds,tx clk out rx clk in,tx out 3/ rx in 3,tx out 2/ rx in 2,tx out 1/ rx in 1,tx out 0/ rx in 0,previous cycle,next cycle,txin5-1 txin27-1 txin23 txin17 txin16 txin11 txin10 txin5 txin27,txin20-1 txin19-1 txin26 txin25 txin24 txin22 txin21 txin20 txin19,txin9-1 txin8-1 txin18 txin15 txin14 txin13 txin12 txin9 txin8,txin1-1 txin0-1 txin7 txin6 txin4 txin3 txin2 txin1 txin0,figure 16. parallel ttl data inputs mapped to lvds outputs (ds90cr583),lvds,host graphics controller,lcd panel controller,txclk in,rxclk out,cmos /ttl,cmos /ttl,fpd link ds90cr583,fpd link ds90cr584,data (lvds),clock (lvds),application,open ldi,ttl parallel-to-lvds,dc balance,dc balance & deskew,lvds -to- ttl parallel,pll,8,8,8,8,8,8,8,8,8,8,8,8,red 1 grn 1 blue 1 red 2 grn 2 blue 2,red 1 grn 1 blue 1 red 2 grn 2 blue 2,fpline fpframe drdy control,fpshift in 32.5 112mhz (170mhz spm),cmos/ttl inputs,ds90c387,ds90c387,pll,lvds data 195 672 mbps per channel,lvds clock (32.5 to 112mhz),5.376gbps,fpline fpframe drdy control,fpshift out 32.5 112mhz,cmos/ttl inputs,the digital interface-tmds,panellink interface (silicon image) transition minimized differential signaling adopted by the lcd monitor interface(open system), and determine the correct sampling point. 10x internal clock &voltage swing = 400 to 600 mv only 4 twisted pairs, support vga to uxga 3 times oversampling the serial data stream code is encoded to provide dc balancing long distance transmission easy (5m) data-to-data skew tolerance 1 clock cycle,tmds,tmds (transition minimized differential signaling)is an interface standard based on panellink technology developed by silicon image, inc.,swing control,encoder/ serialized,pll,graphic controller,termination control,recovery/ decorder/ desirializer,pll,lcd panel,data,data,de,de,controls,controls,clock,clock,tx1(green),tx0(blue),tx2(red),clock,24,5,24/36,5,vcc,vcc,paralle