《通信系统FPGA开发》课程设计-数字钟课程设计.docx

通信系统FPGA开发课程设计任务书 （适用于通信工程专业）1. 设计一数字钟系统，要求如下：(1) 有基础的实时数字钟功能，即时，分，秒的正常显示模式。（24小时制）(2) 可对系统用手动方式校准，设计两个按键，按动校时键，时计数器加一，按动校分键，则电路处于校分状态。(3) 整点报时，要求在59分50秒，52秒，54秒，56秒和58秒发出一个低音信号，00分00秒发出一个高音信号。完整代码加测试代码：module kongzhi_count(clk,S1,S2,reset,hour_s,hour_g,minute_s,minute_g,second_s,second_g,cout_1,cout_2,alarm_clock_low,alarm_clock_high); input clk,S1,S2,reset;output reg3:0 hour_s,hour_g,minute_s,minute_g,second_s,second_g ;output wire cout_1,cout_2;output reg alarm_clock_low,alarm_clock_high;reg R1,R2;always (posedge clk) beginif(S1=1)beginR1=1;endelse if(S2=1)beginR2=1;endendalways (posedge clk) /秒个位显示 begin if(reset) second_g = 0; else if(second_g=9) second_g = 0; else second_g = second_g + 1; end always (posedge clk) /秒十位显示 begin if(reset) second_s= 0; else if(second_g=9) begin if(second_s=5) second_s= 0; else second_s = second_s + 1; end end assign cout_1=(second_g=9)&(second_s=5)?1:0;always (posedge clk) /分个位显示 begin if(reset) begin minute_g = 0; end else if(R2=1) begin if(minute_g=9) minute_g = 0; else begin minute_g= minute_g+ 1; end R2=0; end else if(cout_1) begin second_g=0; second_s=0; if(minute_g=9) minute_g = 0; else minute_g= minute_g+ 1; end end always (posedge clk) /分十位显示 begin if(reset) begin minute_s = 0; end else if(R2=1) begin if(minute_g=9) begin if(minute_s=5) minute_g = 0; else minute_s = minute_s + 1; end R2=0; end else if(cout_1) begin second_g=0; second_s=0; if(minute_g=9) begin if(minute_s=5) minute_g = 0; else minute_s = minute_s + 1; end end endassign cout_2=(minute_g=9)&(minute_s=5)&(cout_1=1)|(minute_g=9)&(minute_s=5)&(S2=1)?1:0;always (posedge clk) /时个位显示 begin if(reset) begin hour_g = 0; end else if(R1=1)beginif(hour_g=9) hour_g = 0; else if(hour_s=2)&(hour_g=3) hour_g = 0; else begin hour_g = hour_g+ 1; end R1=0; end else if(cout_2) begin second_g=0; second_s=0; minute_g=0; minute_s=0; if(hour_g=9) hour_g = 0; else if(hour_s=2)&(hour_g=3) hour_g = 0; else hour_g = hour_g+ 1; end endalways (posedge clk) /时十位显示 begin if(reset) begin hour_s= 0; end else if(R1=1)beginif(hour_g=3)&(hour_s=2) hour_s = 0; else if(hour_g=9) begin hour_s = hour_s + 1; end R1=0; end else if(cout_2) begin second_g=0; second_s=0; minute_g=0; minute_s=0; if(hour_g=3)&(hour_s=2) hour_s = 0; else if(hour_g=9) hour_s = hour_s + 1; end endalways (posedge clk) /低音警报begin if(!reset) begin alarm_clock_low=0; end else if(minute_g=9)&(minute_s=5) if(second_s=4)&(second_g=9)|(second_s=5)&(second_g=1)|(second_s=5)&(second_g=3)|(second_s=5)&(second_g=5)|(second_s=5)&(second_g=7) alarm_clock_low=1; else alarm_clock_low=0; end always (posedge clk) /高音警报begin if(!reset) begin alarm_clock_high=0; end else if(cout_2) alarm_clock_high=1; else alarm_clock_high=0; endendmodulemodule clock_test(); reg clk,reset,S1,S2;wire3:0 hour_s,hour_g,minute_s,minute_g,second_s,second_g;wire cout_1,cout_2,alarm_clock_low,alarm_clock_high;parameter cycle = 100;kongzhi_count u1(.clk(clk),.S1(S1),.S2(S2),.reset(reset),.hour_s(hour_s),.hour_g(hour_g),.minute_s(minute_s),.minute_g(minute_g),.second_s(second_s),.second_g(second_g),.cout_1(cout_1),.cout_2(cout_2),.alarm_clock_low(alarm_clock_low),.alarm_clock_high(alarm_clock_high); always #(cycle/2) clk = clk;