简单的FIFO仿真以及程序.doc

写了一个简单的同步FIFO 的源程序以及Testbench仿真程序。主要参考了特权同学Xilinx fifo的仿真。有图有真相，抛砖引玉。下面是程序：module fifo( clk, rst,/ fifo_wrdb, /din fifo_rddb,/dout fifo_full, fifo_empty);input clk;input rst;/input7:0fifo_wrdb;output fifo_full;output fifo_empty;/ reg fifo_rdrdy;/fifo读数据有效信号output 7:0fifo_rddb;/fifo读数据总线/*/wire 7:0fifo_wrdb_r;/assign fifo_wrdb_r = fifo_wrdb;/定时产生32个FIFO数据写入和读出操作reg7:0 fifo_wrdb;/FIFO写入数据reg fifo_wren;/FIFO写使能信号reg fifo_rden;/FIFO读使能信号reg9:0 cnt;always (posedge clk or negedge rst)if(!rst) cnt = 10d0;else cnt = cnt+1b1;always (posedge clk or negedge rst )if(!rst) beginfifo_wren = 1b0;fifo_rden = 1b0;fifo_wrdb 10d0) & (cnt 10d33) begin/连续32个FIFO数据写入fifo_wren = 1b1;fifo_rden = 1b0;fifo_wrdb 10d100) & (cnt 10d133) begin/连续32个FIFO数据读出fifo_wren = 1b0;fifo_rden = 1b1;fifo_wrdb = 8d0;endelse beginfifo_wren = 1b0;fifo_rden = 1b0;fifo_wrdb = 8d0;end/*/FIFO读数据有效标志位/ always (posedge clk or negedge rst)/if(rst) fifo_rdrdy = 1b0;/else fifo_rdrdy = fifo_rden;/*/fifo_controller fifo_controller_ck( .clk(clk), / input clk .rst(rst), / input rst .din(fifo_wrdb), / input 7 : 0 din .wr_en(fifo_wren), / input wr_en .rd_en(fifo_rden), / input rd_en .dout(fifo_rddb), / output 7 : 0 dout .full(fifo_full), / output full .empty(fifo_empty) / output empty);endmodule下面是仿真程序：module fifo_text;/ Inputsreg clk;reg rst;/ Outputswire 7:0 fifo_rddb;wire fifo_full;wire fifo_empty;/ Instantiate the Unit Under Test (UUT)fifo uut (.clk(clk), .rst(rst), .fifo_rddb(fifo_rddb), .fifo_full(fifo_full), .fifo_empty(fifo_empty);initial begin/ Initialize Inputsclk = 1b0; rst = 1b0;/fifo_wrdb = 1;/ Wait 100 ns for global reset to finish#100; rst = 1b1;