惠普NC 4400笔记本图纸.pdf

A A B B C C D D E E 11 22 33 44 Title SizeDocument NumberRev Date:Sheetof Security ClassificationCompal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued DateDeciphered Date LA-3031 0.2 Cover Sheet 147Tuesday, October 11, 2005 2005/10/112006/10/11 Compal Electronics, Inc. REV:0.2 Schematics Document 2005-10-11 Compal confidential Mobile Yonah uFCPGA with Intel Calistoga_GM+ICH7-M core logic Oct 11, 2006 A A B B C C D D E E 11 22 33 44 Title SizeDocument NumberRev Date:Sheetof Security ClassificationCompal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued DateDeciphered Date LA-3031 0.2 Block Diagram 247Tuesday, October 11, 2005 2005/10/112006/10/11 Compal Electronics, Inc. Power On/Off CKT. File Name : LA-3031 LPC BUS page 27 Compal confidential page 19 H_A#(3.31) CardBus Controller H_D#(0.63) TI PCI6612 page 28 BANK 0, 1, 2, 3 USB conn x3 DMI page 22,23 DC/DC Interface CKT. page 34 USB2.0 FSB Clock Generator Power Circuit DC/DC PCI BUS page 33 DDR-SO-DIMM X2 page 35 page 4 page 4,5,6 RTC CKT. Audio CKT page 15 page 36 page 4 page 7,8,9,10,11,12 Thermal Sensor ADM1032AR page 13,14 page 18,19,20,21 Docking CONN. *RJ-45(LED*2) *RJ-11(Pass Through) *CRT *COMPOSITE Video Out *TVOUT *DVI *LINE IN *LINE OUT *PCI-E x1 *Serial Port *Parallel Port *PS/2 x2 *USB x2 *DC JACK AMP & Audio Jack Power OK CKT. page 19 Slot 0 page 23 Heavenly 2.0 BT Conn page 17 DOCK/DVI page 34 CH7307C-DE Fan Control SDVO CRT/TV-OUT Dual Channel SST49LF008A Flash ROMSecurity Module Touch Pad CONN.Int.KBD SD/SDIO Slot LCD CONN DVI controller page 22 page 31 page 32 Digitizer page 33 page 17 page 33 page 31 36,37,38,39,40,41,42,43 page 26 Mini Card socket page 24 page 25 Gigabit LAN BCM5753M RJ45/11 CONN PCI-E BUS Mobile Yonah & Merom uFCPGA-478 CPU PCBGA 1466 Intel Calistoga GMCH 945GM DDR2 -400/533/667 533/667MHz ICS9LP306 mBGA-652 Intel ICH7-M SMSC KBC 1021 SPI 25LF080A SPI ROM page 31 SATA Master SATA HDD Connector AD1981HD AC-LINK/Azalia page 31 MDC1.5 FingerPrinter AES2501 page 29 FIR page 30 LPT on Docking side LPC47N217 COM1 on Docking side SMSC Super I/O page 30 page 16 page 17page 29 page 29 page 30 page 30 A A 11 Title SizeDocument NumberRev Date:Sheetof Security ClassificationCompal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued DateDeciphered Date LA-3031 0.2 Notes List 347Tuesday, October 11, 2005 2005/10/112006/10/11 Compal Electronics, Inc. ? ? VIN ? ? O FF Power Plane N/AN/A ? ? ? ? ? ? ? ON AC or battery power rail for power circuit ? ? ? +CPU_CORE +0.9VS S3 ? +1.5VS ? ? ? O FF +VCCP ? ? N/A ? ? ? ? ? ? ? ? Internal PCI Devices ? ? ? ? ? I2C / SMBUS ADDRESSING ? ? ? ? ? ON ? ? ? ? ? ? ? ? ? ? ? ? ? ?!? ? ? ? ? # ?$? ? % &?$ ? ? ? ? ? ? 0.9V switched power rail for DDRII Vtt S0-S1 ?( ? ONO FF ON ? ?)*? +)? ? N/A N/A ? ? ?,? O FF ? ?)*? +)? ? Description ? ? ? ? ? ?,? 1.05V power rail for Processor I/O and MCH core power ? - ? ? # ? - ? ?% Adapter power supply (19V) ? ? ? ? ? ? ? ? External PCI Devices ? N/A ?.? ? ? ? O FF ? O FF ?,? Core voltage for CPU O FF ? O FF ? . S5 ? 1.5V switched power rail for PCI-E interface B+ Voltage RailsSymbol note: :means digital ground. :means analog ground. :means reserved. ON O FF2.5V switched power rail for MCH video PLL 5V always on power rail ON 3.3V always on power rail 3.3V switched power rail+3VS ON* +5V O FF RTC power +3V ONON Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. +1.8V O FF ON O FF ON ON +3VALW O FF ON 5V switched power rail ON +2.5VS RTCVCC +5VS ON 5V power rail ONO FF ON ON 3V power rail O FF O FF ON +5VALW ON 1.8V power rail for DDRII ON* O FF ON ON2.5V always on power rail+2.5VALWON*ON ? ? ?/01 ? 0? ? ? ? ? ? ? ? ?2 ? ? ?2 ?2 # ? 3 041 )? 45? ?% # ? ? ? 3 ? ? 3 041 )? 45? ?% # ? 3 041 )? 45? ?% 45 : means need be mounted when 45 level assy or rework stage. 250 : means just build when SMsC LPC47N250 chip selected. : means just reserve , no build SPI : means just build when SPI I/F BIOS function enable. NOXDP : means just build when XDP function disable. XDP : means just build when XDP function enable. When this time, docking PCI express will not work. TPM : means just build when TPM1.2 function enable. FWH : means just build when FWH I/F BIOS function enable. ACCEL : means just build when Accelerometer chip LIS3LV02DQ selected. 1021 : means just build when SMsC KBC1021 chip selected. DVI_7307 : means just build when DVI chip CH7307 selected. DVI_1362 : means just build when DVI chip SIL1362 selected. 5 5 4 4 3 3 2 2 1 1 DD CC BB AA H_A#28 H_THERMDA H_FERR# H_ADSTB#0 H_A#23 H_REQ#2 H_A#31 H_REQ#0 H_A#17 H_BNR# H_A#29 H_DSTBP#0 H_A#8 H_DEFER# H_REQ#1 H_A#3 H_RS#0 H_DSTBN#1 H_A#6 XDP_BPM#2 H_BPRI# H_ADS# H_A#25 XDP_BPM#3 H_RS#1 H_DSTBP#1 H_A#4 H_IERR# H_HITM# H_DSTBN#0 H_INTR H_DSTBN#2 H_A#22 H_A#7 H_REQ#4 XDP_DBRESET# H_DRDY# H_A#15 H_A#14 H_A20M# H_DINV#0 H_DSTBP#2 H_DINV#2 H_DINV#3 H_DINV#1 H_DSTBN#3 H_DSTBP#3 H_NMI H_A#30 H_A#27 H_A#18 H_A#10 H_BR0# H_LOCK# H_A#11 H_A#21 H_A#26 H_A#13 H_A#9 XDP_BPM#0 H_DPSLP# H_A#20 H_A#16 H_A#12 H_HIT# H_ADSTB#1 H_THERMTRIP# H_DBSY# H_A#19 H_A#24 H_A#5 H_RS#2 H_RESET# XDP_BPM#1 H_REQ#3 H_SMI# H_STPCLK# XDP_TCK XDP_TRST# H_CPUSLP# XDP_TDO XDP_TDI H_PWRGOOD XDP_BPM#5 H_DPRSTP# H_TRDY# CLK_CPU_BCLK CLK_CPU_BCLK# H_THERMDC XDP_BPM#4 H_DPWR# TEST1 TEST2 H_D#0 H_D#1 H_D#2 H_D#3 H_D#7 H_D#6 H_D#4 H_D#5 H_D#11 H_D#10 H_D#8 H_D#9 H_D#15 H_D#14 H_D#12 H_D#13 H_D#19 H_D#18 H_D#16 H_D#17 H_D#23 H_D#22 H_D#20 H_D#21 H_D#27 H_D#26 H_D#24 H_D#25 H_D#31 H_D#30 H_D#28 H_D#29 H_D#35 H_D#34 H_D#32 H_D#33 H_D#39 H_D#38 H_D#36 H_D#37 H_D#43 H_D#42 H_D#40 H_D#41 H_D#47 H_D#46 H_D#44 H_D#45 H_D#51 H_D#50 H_D#48 H_D#49 H_D#55 H_D#54 H_D#52 H_D#53 H_D#59 H_D#58 H_D#56 H_D#57 H_D#63 H_D#62 H_D#60 H_D#61 H_INIT# H_IGNNE# H_PROCHOT# H_PROCHOT#OCP# XDP_BPM#3 ICH_SMBDATA ICH_SMBCLK XDP_BPM#2 XDP_DBRESET#_R XDP_BPM#1 XDP_BPM#0 XDP_PRE XDP_DBRESET#XDP_DBRESET#_R XDP_TCK XDP_TDI XDP_TMS XDP_TRST# XDP_TCK XDP_TRST# XDP_TMS XDP_TDI XDP_TDO H_RESET#H_RESET#_R H_PWRGOOD_RH_PWRGOODCLK_CPU_XDP CLK_CPU_XDP# XDP_BPM#4 XDP_BPM#5 XDP_BPM#5 FAN THERM# ICH_SMBCLK ICH_SMBDATA H_THERMDA H_THERMDCTHERM_SCI# THERM# ICH_SMBDATA ICH_SMBCLK XDP_TDO XDP_TMS H_D#0.63 7 H_A#3.317 H_REQ#0.47 H_ADSTB#07 H_ADSTB#17 CLK_CPU_BCLK#15 CLK_CPU_BCLK15 H_ADS#7 H_BNR#7 H_BR0#7 H_DRDY#7 H_HIT#7 H_HITM#7 H_BPRI#7 H_DEFER#7 H_LOCK#7 H_RESET#7 H_RS#0.27 H_TRDY#7 H_DBSY#7 H_DPSLP#19 H_DPRSTP#19,43 H_DPWR#7 H_CPUSLP#7 H_THERMTRIP#7,19 H_DINV#0 7 H_DINV#1 7 H_DINV#2 7 H_DINV#3 7 H_DSTBN#0.3 7 H_DSTBP#0.3 7 H_A20M#19 H_FERR# 19 H_IGNNE# 19 H_INIT#19 H_INTR19 H_NMI19 H_STPCLK# 19 H_SMI#19 XDP_DBRESET#20 H_PROCHOT#43 OCP#20,44 CLK_CPU_XDP 15 CLK_CPU_XDP# 15 H_PWRGOOD19 FAN_PWM32 ICH_SMBDATA13,14,15,20,24,26 ICH_SMBCLK13,14,15,20,24,26 THERM_SCI# 20 +VCCP +VCCP +VCCP +3VS +VCCP+VCCP +VCCP +5VS +3VS +3VS +3VS +VCCP Title SizeDocument NumberRev Date:Sheetof Security ClassificationCompal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued DateDeciphered Date LA-3031 0.2 Yonah CPU in mFCPGA479 447Tuesday, October 11, 2005 2005/10/112006/10/11 Compal Electronics, Inc. H_THERMDA, H_THERMDC routing together. Trace width / Spacing = 10 / 10 mil ITP-XDP Connector This shall place near CPU PWM Fan Control circuit Thermal Sensor ADM1032 Address:1001_101 This shall place near JP19 7/14 7/19 7/28 9/2 R558 200_0402_1% 12 ADDR GROUP CONTROL HOST CLK MISC DATA GROUP THERMAL DIODE LEGACY CPU YONAH JP12A FOX_PZ47903-2741-42_YONAH A3# J4 A4# L4 A5# M3 A6# K5 A7# M1 A8# N2 A9# J1 A10# N3 A11# P5 A12# P2 A13# L1 A14# P4 A15# P1 A16# R1 A17# Y2 A18# U5 A19# R3 A20# W6 A21# U4 A22# Y5 A23# U2 A24# R4 A25# T5 A26# T3 A27# W3 A28# W5 A29# Y4 A30# W2 A31# Y1 REQ0# K3 REQ1# H2 REQ2# K2 REQ3# J3 REQ4# L5 ADSTB0# L2 ADSTB1# V4 BCLK0 A22 BCLK1 A21 ADS# H1 BNR# E2 BPRI# G5 BR0# F1 DEFER# H5 DRDY# F21 HIT# G6 HITM# E4 IERR# D20 LOCK# H4 RESET# B1 RS0# F3 RS1# F4 RS2# G3 TRDY# G2 BPM0# AD4 BPM1# AD3 BPM2# AD1 BPM3# AC4 DBR# C20 DBSY# E1 DPSLP# B5 DPWR# D24 PRDY# AC2 PREQ# AC1 PROCHOT# D21 PWRGOOD D6 SLP# D7 TCK AC5 TDI AA6 TDO AB3 TEST1 C26 TEST2 D25 TMS AB5 TRST# AB6 THERMDA A24 THERMDC A25 THERMTRIP# C7 D0# E22 D1# F24 D2# E26 D3# H22 D4# F23 D5# G25 D6# E25 D7# E23 D8# K24 D9# G24 D10# J24 D11# J23 D12# H26 D13# F26 D14# K22 D15# H25 D16# N22 D17# K25 D18# P26 D19# R23 D20# L25 D21# L22 D22# L23 D23# M23 D24# P25 D25# P22 D26# P23 D27# T24 D28# R24 D29# L26 D30# T25 D31# N24 D32# AA23 D33# AB24 D34# V24 D35# V26 D36# W25 D37# U23 D38# U25 D39# U22 D40# AB25 D41# W22 D42# Y23 D43# AA26 D44# Y26 D45# Y22 D46# AC26 D47# AA24 D48# AC22 D49# AC23 D50# AB22 D51# AA21 D52# AB21 D53# AC25 D54# AD20 D55# AE22 D56# AF23 D57# AD24 D58# AE21 D59# AD21 D60# AE25 D61# AF25 D62# AF22 D63# AF26 DINV0# J26 DINV1# M26 DINV2# V23 DINV3# AC20 DSTBN0# H23 DSTBN1# M24 DSTBN2# W24 DSTBN3# AD23 DSTBP0# G22 DSTBP1# N25 DSTBP2# Y25 DSTBP3# AE24 A20M# A6 FERR# A5 IGNNE# C4 INIT# B3 LINT0 C6 LINT1 B4 STPCLK# D5 SMI# A3 DPRSTP# E5 R5621K_0402_5% 12 C5900.1U_0402_16V4Z 12 R55256_0402_5% 12 D11 CH751H-40_SC76 21 C933 1000P_0402_50V7K 1 2 R557 1K_0402_1% 12 R560 56_0402_5% 12 JP19 SAMTE_BSH-030-01-L-D-A GND0 1 OBSFN_A0 3 OBSFN_A1 5 GND2 7 OBSDATA_A0 9 OBSDATA_A1 11 GND4 13 OBSDATA_A2 15 OBSDATA_A3 17 GND6 19 OBSFN_B0 21 OBSFN_B1 23 GND8 25 OBSDATA_B0 27 OBSDATA_B1 29 GND10 31 OBSDATA_B2 33 OBSDATA_B3 35 GND12 37 PWRGOOD/HOOK0 39 HOOK1 41 VCC_OBS_AB 43 HOOK2 45 HOOK3 47 GND14 49 SDA 51 SCL 53 TCK1 55 TCK0 57 GND16 59 GND1 2 OBSFN_C0 4 OBSFN_C1 6 GND3 8 OBSDATA_C0 10 OBSDATA_C1 12 GND5 14 OBSDATA_C2 16 OBSDATA_C3 18 GND7 20 OBSFN_D0 22 OBSFN_D1 24 GND9 26 OBSDATA_D0 28 OBSDATA_D1 30 GND11 32 OBSDATA_D2 34 OBSDATA_D3 36 GND13 38 ITPCLK/HOOK4 40 ITPCLK#/HOOK5 42 VCC_OBS_CD 44 RESET#/HOOK6 46 DBR#/HOOK7 48 GND15 50 TD0 52 TRST# 54 TDI 56 TMS 58 GND17 60 R561 68_0402_5% 1 2 R56351_0402_5% 12 R55056_0402_5% 12 U24 TC7SH00FUF_SSOP5 INB 1 INA 2 O 4 G 3 P 5 R55356_0402_5% 12 R55156_0402_1% 12 C122 4.7U_0805_10V4Z 1 2 R55556_0402_5% 12 R227 10K_0402_5% 12 JP8 ACES_85205-0200 1 2 R559 0_0402_5% 12 C932 1000P_0402_50V7K 1 2 E B C Q73 MMBT3904_SOT23 2 31 C125 0.1U_0402_16V4Z 1 2 U16 ADM1032ARMZ-2REEL MSOP8 VDD 1 ALERT# 6 THERM# 4 GND 5 D+ 2 D- 3 SCLK 8 SDATA 7 C264 2200P_0402_50V7K 12 R55456_0402_5% 12 R564 56_0402_5% 12 R556 1K_0402_5% 12 C273 0.1U_0402_16V4Z 1 2 ZD1 RLZ5.1B_LL34 12 S G D Q33 AO6402_TSOP6 3 6 2 45 1 R549 1K_0402_5% 12 R228 10K_0402_5% 12 5 5 4 4 3 3 2 2 1 1 DD CC BB AA COMP3 COMP2 H_PSI# COMP1 COMP0 CPU_VID1 CPU_VID0 CPU_VID3 CPU_VID4 CPU_VID2 CPU_VID5 CPU_VID6 CPU_BSEL1 CPU_BSEL2 CPU_BSEL0 VSSSENSE VCCSENSE VSSSENSE VCCSENSE H_PSI#43 CPU_VID043 CPU_VID143 CPU_VID243 CPU_VID343 CPU_VID443 CPU_VID543 CPU_VID643 CPU_BSEL015 CPU_BSEL115 CPU_BSEL215 VCCSENSE43 VSSSENSE43 +VCCP +VCC_CORE +VCCP V_CPU_GTLREF V_CPU_GTLREF +1.5VS +VCC_CORE +VCC_CORE Title SizeDocument NumberRev Date:Sheetof Security ClassificationCompal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued DateDeciphered Date LA-3031 0.2 Yonah CPU in mFCPGA479 547Tuesday, October 11, 2005 2005/10/112006/10/11 Compal Electronics, Inc. Resistor placed within 0.5 of CPU pin.Trace should be at least 25 mils away from any other toggling signal. Close to CPU pin AD26 within 500mils. CPU_BSELCPU_BSEL2CPU_BSEL1 133 166 00 0 1 CPU_BSEL0 1 1 Length match within 25 mils The trace width 18 mils space 7 mils Close to CPU pin within 500mils. R567 1K_0402_1% 12 C592 10U_0805_10V4Z 1 2 R569 100_0402_1% 12 POWER, GROUND YONAH JP12C FOX_PZ47903-2741-42_YONAH VCC AE18 VCC AE17 VCC AB15 VCC AA15 VCC AD15 VCC AC15 VCC AF15 VCC AE15 VCC AB14 VCC AA13 VCC AD14 VCC AC13 VCC AF14 VCC AE13 VCC AB12 VCC AA12 VCC AD12 VCC AC12 VCC AF12 VCC AE12 VCC AB10 VCC AB9 VCC AA10 VCC AA9 VCC AD10 VCC AD9 VCC AC10 VCC AC9 VCC AF10 VCC AF9 VCC AE10 VCC AE9 VCC AB7 VCC AA7 VCC AD7 VCC AC7 VCC B20 VCC A20 VCC F20 VCC E20 VCC B18 VCC B17 VCC A18 VCC A17 VCC D18 VCC D17 VCC C18 VCC C17 VCC F18 VCC F17 VCC E18 VCC E17 VCC B15 VCC A15 VCC D15 VCC C15 VCC F15 VCC E15 VSS K1 VSS J2 VSS M2 VSS N1 VSS T1 VSS R2 VSS V2 VSS W1 VSS A26 VSS D26 VSS C25 VSS F25 VSS B24 VSS A23 VSS D23 VSS E24 VSS B21 VSS C22 VSS F22 VSS E21 VSS B19 VSS A19 VSS D19 VSS C19 VSS F19 VSS E19 VSS B16 VSS A16 VSS D16 VSS C16 VSS F16 VSS E16 VSS B13 VSS A14 VSS D13 VSS C14 VSS F13 VSS E14 VSS B11 VSS A11 VSS D11 VSS C11 VSS F11 VSS E11 VSS B8 VSS A8 VSS D8 VSS C8 VSS F8 VSS E8 VSS G26 VSS K26 VSS J25 VSS M25 VSS N26 VSS T26 VSS R25 VSS V25 VSS W26 VSS H24 VSS G23 VSS K23 VSS L24 VSS P24 VSS N23 VSS T23 VSS U24 VSS Y24 VSS W23 VSS H21 VSS J22 VSS M22 VSS L21 VSS P21 VSS R22 VSS V22 VSS U21 VSS Y21 VCC B14 VCC A13 VCC D14 VCC C13 VCC F14 VCC E13 VCC B12 VCC A12 VCC D12 VCC C12 VCC F12 VCC E12 VCC B10 VCC B9 VCC A10 VCC A9 VCC D10 VCC D9 VCC C10 VCC C9 VCC F10 VCC F9 VCC E10 VCC E9 VCC B7 VCC F7 VCC A7 R568 100_0402_1% 12 R570 2K_0402_1% 12 POWER, GROUNG, RESERVED SIGNALS AND NC YONAH JP12B FOX_PZ47903-2741-42_YONAH PSI# AE6 GTLREF AD26 VCCSENSE AF7 VCCA B26 VCC AB20 VCC AA20 VCC AF20 VCC AE20 VCC AB18 VCC AB17 VCC AA18 VCC AA17 VCC AD18 VCC AD17 VCC AC18 VCC AC17 VCC AF18 VCC AF17 RSVD T22 RSVD V3 RSVD B2 RSVD C3 VSS AB26 VSS AA25 VSS AD25 VSS AE26 VSS AB23 VSS AC24 VSS AF24 VSS AE23 VSS AA22 VSS AD22 VSS AC21 VSS AF21 VSS AB19 VSS AA19 VSS AD19 VSS AC19 VSS AF19 VSS AE19 VSS AB16 VSS AA16 VSS AD16 VSS AC16 VSS AF16 VSS AE16 VSS AB13 VSS AA14 VSS AD13 VSS AC14 VSS AF13 VSS AE14 VSS AB11 VSS AA11 VSS AD11 VSS AC11 VSS AF11 VSS AE11 VSS AB8 VSS AA8 VSS AD8 VSS AC8 VSS AF8 VSS AE8 VSS AA5 VSS AD5 VSS AC6 VSS AF6 VSS AB4 VSS AC3 VSS AF3 VSS AE4 VSS AB1 VSS AA2 VSS AD2 VSS AE1 VSS B6 VSS C5 VSS F5 VSS E6 VSS H6 VSS J5 VSS M5 VSS L6 VSS P6 VSS R5 VSS V5 VSS U6 VSS Y6 VSS A4 VSS D4 VSS E3 VSS H3 VSS G4 VSS K4 VSS L3 VSS P3 VSS N4 VSS T4 VSS U3 VSS Y3 VSS W4 VSS D1 VSS C2 VSS F2 VSS G1 RSVD B25 VSSSENSE AE7 VCCP K6 VCCP J6 VCCP M6 VCCP N6 VCCP T6 VCCP R6 VCCP K21 VCCP J21 VCCP M21 VCCP N21 VCCP T21 VCCP R21 VCCP V21 VCCP W21 VCCP V6 VCCP G21 VID0 AD6 VID1 AF5 VID2 AE5 VID3 AF4 VID4 AE3 VID5 AF2 VID6 AE2 BSEL0 B22 BSEL1 B23 BSEL2 C21 COMP0 R26 COMP1 U26 COMP2 U1 COMP3 V1 RSVD C23 RSVD C24 RSVD AA1 RSVD AA4 RSVD AB2 RSVD AA3 RSVD M4 RSVD N5 RSVD T2 RSVD D2 RSVD F6 RSVD D3 RSVD C1 RSVD AF1 RSVD D22 VCC E7 R574 54.9_0402_1% 12 R573 27.4_0402_1% 12 C591 .01U_0402_16V7K 1 2 R571 27.4_0402_1% 12 R572 54.9_0402_1% 12 5 5 4 4 3 3 2 2 1 1 DD CC BB AA +VCCP +VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE Title SizeDocument NumberRev Date:Sheetof Security ClassificationCompal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued DateDeciphered Date LA-3031 0.2 CPU Bypass capacitors 647Tuesday, October 11, 2005 2005/10/112006/10/11 Compal Electronics, Inc. Mid Frequence Decoupling ESR = 1.5m ohm Capacitor = 1980uF South Side Secondary Place these inside socket cavity on L8 (North side Secondary) North Side Secondary Place these capacitors on L8 (North side,Secondary Layer) Place these capacitors on L8 (Sorth side,Secondary Layer) Place these capacitors on L8 (Sorth side,Secondary Layer) Place these capacitors on L8 (North side,Secondary Layer) C596 10U_0805_6.3V6M 1 2 C637 0.1U_0402_16V4Z 1 2 C603 10U_0805_6.3V6M 1 2 C620 10U_0805_6.3V6M 1 2 C609 10U_0805_6.3V6M 1 2 + C629 330U_D2E_2.5VM_R9 1 2 C639 0.1U_0402_16V4Z 1 2 C638 0.1U_0402_16V4Z 1 2 C617 10U_0805_6.3V6M 1 2 C602 10