高速运算放大器外文翻译.docx

杭州电子科技大学信息工程学院毕业设计（论文）外文文献翻译毕业设计（论文）题目高速运算放大器设计翻译题目高速运算放大器架构的演进系电子工程专 业电子信息工程姓 名袁浙娜班 级08091912学 号08918205指导教师邝小飞高速运算放大器架构的演进一、摘要通过对现代宽带双极晶体管运算放大器的长处和弱点进行调查，并在带宽，压摆率，失真和功耗方面进行比较。本文从真空管随着时间的推移以及大量使用的角度追溯运算放大器设计的演变.其特殊的价值在于能够使设计师以这些电路的设计方案为基础应用于许多新的放大器的设计.此外，还描述了一个编造ATT CBIC V2的过程中运算放大器的组件数组。本设计采用那些经过多年发展的设计技术，在一个单独的晶圆上,产生四个独立运算放大器。工艺设计方面主要需要确定每个架构的共同元素和阵列上,实现四个独特的架构所需的额外组件的最低数量。这项工作主要是通过审查各种拓扑结构，以及利用以前的设计，然后以几种不同的设计和制造特殊的基础阵列来证明设计是如何工作的。在集成电路出现之前已经存在运算放大器，但是似乎当与性能最佳的互补双极型工艺相匹配时，这些设备的性能还是有所限制的。反过来，为了使这些运算放大器得到更好的应用，需要越来越高的性能的电路设计和工艺技术的发展，以满足每一个新的需求。在第II IV章节中，主要对现代高速+/- 5- V的运算放大器设计的几个方面进行了讨论。电压反馈和电流反馈拓扑架构是如何随着时间而演变的，特别强调所发现的问题是如何解决的。以及对多级放大器，单位增益缓冲器，低功耗和低失真的设计问题的解决方案进行审查。在第VI- VIII章，详细的分析给出的四个不同的高速，高性能放大器，如何完全实施在一个芯片上，以降低开发成本。在这项工作中的许多电路都涵盖了美国和其他国家保护的专利。一些显著的专利来源被引用，尤其是在专利文件中是作者出版的唯一来源。二、电流反馈放大器电流反馈的概念可以追溯到20世纪40年代的真空管设计，并早在20世纪60年代的离散晶体管的仪表放大器设计中已经得到实施。这些设计主要是低增益带宽，即A类的实现，没有提供今天的电流反馈放大器的特点高压摆率。高压摆可以达到一些电流反馈设计自摆电流，并与输入电压成正比。传统的差分放大器存在输入级的偏置电流，固定设置了回转的电流量的限制。20世纪80年代带来了即现在熟悉的单级水平位移电流反馈放大器，是最初威尔逊电流镜注入一个补偿电容当前摆而来。（图3）虽然这种拓扑结构简单，工作的很好，但有些相位裕度由于通过镜子的传播而延迟。此外，还有一个趋势即放大器尝试由于内部的集电极电阻，二极管连接晶体管电流镜自饱和时，提供峰值摆电流。虽然单级电流反馈拓扑结构是非常受欢迎的，但是可接受的开环阻总是不够高。而要达到更高的开环阻的就要添加另一个阶段。然而，第二阶段的稳定偏置是一个复杂的问题，并且带宽几乎总是被牺牲。也许第一次公开表明的两阶段电流反馈放大器如图4所示。根据设计，它缺乏一个直流电流源偏置，在第二阶段自动设置偏置电流反馈环路被关闭。相反，直流偏置电压是可以被检测到并可以同参考电压相比较。不同的是因为高开环增益递过来一个缓慢的直流偏置稳定点。并且获得的开环阻超过2欧姆。三、电压反馈放大器在过去的十年中，电流反馈高速放大器设计成为主要的选择，然而，最近电压反馈有重新抬头的趋势。电压反馈提供的几个特点是电流反馈高速放大器所没有的，如在低增益低噪音，低级别的设置，设计反相集成性能等方面，如增益带宽和低噪音的要求最终应用于有源滤波器的程序中，尽管有较长时间的历史，如图10的单级折叠级联设计所展示的。唯一的继承和共同点就是PNP发射极，虽然他们贡献很小，但这个放大器的小信号带宽是优秀的。在利用电流反馈不断增加速度的同时，现代的互补双极型工艺电压反馈放大器，也以获得较为温和的频率较高的开环增益。这些放大器提供14至18- B的线性度，即现在在信号处理应用时需求的500kHz至20MHz的信号范围的要求。然而，如果没有一个好的方法去做一些相位补偿，每个增益级放大器的潜在带宽都会下降四、单位增益缓冲器尽管增益的配置在1V / V，但是一个单位增益放大器的电压和电流反馈放大器还是可以提供很大的灵活性。典型的应用，推动电缆或闪速转换器的设计是独特的，最大的全功率带宽是需要加驱动较大的负载电容的能力相适应的。期最主要的优势是致力于通过外部反馈网络使内部避免延迟。为了评估一个专用的缓冲区的相对性能的表现，通过三个典型800MHz的单位增益缓冲器的例子进行比较研究。如果反馈是连接包外的，可能看起来像一个标准的8引脚SOIC型，如一个简化的总寄生负载模型模拟。图.16.17显示说明这三种情况。case17（a）是那里有没有寄生的带宽积,case17（b）是带宽积反馈连接外面包，在电路板上包上; case17（c）是片上带宽积与反馈关闭。虽然17（c）显示了一些闭环响应峰值，但显然已经是一个很大的改进了。最后一种方法，是一个单位增益放大器提供一个开环输出，如图19所示。在这种情况下，不仅是反馈连接到芯片上，电容驱动晶体管的分贝值也因反馈点而隔离出来。输出电阻不减少的环路增益不再，虽然它是由偏置电流驱动晶体管反馈调节，并且可任意降低。此外，带宽不是一个负载电容的直接功能。最后，反馈回路不断的偏移量保持在相对较低的数值。五、双极型放大器的失真 放大器的谐波和互调失真一直被模拟设计师高度关注。也许针对低失真的设计，最好的办法是分开来解决每个失真源。此外，尽管存在明显的差异，但电压和电流反馈放大器的失真机制有着惊人的相似性。首先，考虑输出阶段。A类输出级（图20）尽管取得了一些伪科学研究，若相反则会引起失真，并且产生的谐波都是奇数和偶数。忽视非线性，然后第二次和第三次谐波失真方程分别是：至少每个谐波都包含输入电压（VIN），负载电阻（RL），隐含的额定功率耗散（IE）。事实上，这是真正的最失真机制。在大多数设计中，峰值输入电压和负载电阻是固定的，这样的静态电流线性减小，使变形成倍增加。六、用于制造四个放大器的单芯片基阵列考虑到这一背景，需要在一个共同的基础芯片上制造独特的组件阵列。基阵列的晶体管，电阻，电容组成的，是四合一最先进的运算放大器，具有高度的不同特点。这种方法被选中是因为它最大限度地提高了设计工作的效率同时大幅度降低开发成本。这种方法需要确定共同要素，在每个设备的架构时同时加入了额外的电路只形成四种不同的架构。每个放大器在一些重要领域，如带宽，失真，压摆率，和功耗方面都进行了优化。运算放大器可在图.26所示的主要内容以框图的形式表示。每个架构使用所有这些块的一种方式是通过分享他们的共同元素，但这块是针对个别放大器的要求设计的。表一显示了每个放大器架构的重要指标之间的对比。在项目的早期阶段，选择的过程中，使产品性能在基础上得到区分是一项重要的决定。另一个令人信服的理由，强调性能，抵消表面包装，由于需要同时容纳4个不同的设计是不是最佳的芯片尺寸。ATT的CBIC - V2的过程是选择达到预期的性能。表二显示了这一过程的重要特征摘要。七、差分放大器架构通过图30图27显示的简化已经实施的四个差分业务结构示意图。最宽的带宽架构是折叠式共源共栅结构，并在图27所示。因为有一个较少的二级极点比一个典型的多级放大器的相位裕度，带宽的最大化。作为一个单级放大器，形成主导极点增益级和补偿电容的输出阻抗。图28显示了低失真放大器的简化原理图，它具有最高的开环增益，并由于其平衡性达到最低的偏移。低，高频率的失真是凭借第二个阶段采用双积分反馈循环获得的，从而减少第二阶段和输出级的失真。在图29所示的放大器是电流反馈,是所有不同配置中获得压摆率最高的.这种电流反馈放大器的带宽通常是独立的增益，不像电压反馈放大器的带宽与增益设置不同。在图30所示的低功耗放大器也使用的折叠共源共栅结构，即使功耗约为高功率版本的三分之一，带宽也只有减少了一半。该放大器偏置电流降低导致噪声性能很差。这是一个众所周知的事实，适当和充足的电力供应电容绕过运算放大器的稳定是必不可少的。寄生电源电感有一种倾向，提供了积极的内部反馈路径，最好的情况是将减少相位幅度，最坏的情况是会导致振荡。由于放大器的单位增益带宽加大，电源寄生电感减小放大器的电容是列入50 PF片上的旁路电容。虽然在芯片面积大幅无偿支付的前提下，它最终允许标准运算放大器的是8 - pin的封装和引脚输出，以提供超过1 GHz的带宽。八、结论“从来不要抛弃任何东西”，是最能说明运算放大器的进化发展的短语。回顾发达国家近一个半世纪前的电路，今天的设计师有一个庞大的运算放大器供应电路在实施新的设计时用于参考借鉴。本文追溯了一个真正的设计应用程序，它使用许多电路和开发的技术，随着时间的推移演变。最终的结果是不仅为设计师节省时间，降低开发成本，还促使设计师使用最先进的加工技术开发最先进的运算放大器。原文：Evolution of high-speed operational amplifier architecturesAbstract-Strengths and weaknesses of modern wide-bandwidth bipolar transistor operational amplifiers are investigated and compared with respect to bandwidth, slew rate, noise, distortion, and power. This paper traces the evolution of operational amplifier designs since vacuum tube days to give a perspective of the large number of circuit variations used over time. Of particular value is the ability to use many of these circuit design options as the basis of new amplifiers. In addition, an array of operational amplifier components fabricated on the AT&T CBIC V2 process is described. This design incorporates many of the architectural techniques that have evolved over the years to produce four separate operational amplifier on a single base wafer. The process design methodology requires identifying the common elements in each architecture and the minimum number of additional components required to implement four unique architectures on the arrayI. Introduction：The approach to this work will be to review various topologies, to utilize previous designs, and then to fabricate several different designs on the special base array and to demonstrate hoe the designs work. Operational amplifiers have been present since before the dawn of integrated circuits, yet there seem to be few limits to the performance that can e obtained from these devices when matched with the optimum complementary bipolar manufacturing processes. Applications for these operational amplifiers, in turn, demand ever higher performance as the circuit design and process technologies evolve to meet each new demand.In Sections II-IV, several aspects of modern high-speed+/-5-V operational amplifier design are discussed. Voltage-feedback and current-feedback topologies are addressed with special emphasis on how architectures have evolved over time. Multistage amplifiers, unity-gain buffers, and solutions to the low-power and low-distortion design problems are reviewed.In Sections VI-X, a detailed analysis is given of four distinct high-speed, high-performance amplifiers which were fully implemented on one base chip to reduce development cost. Thus, the amplifiers differ only in the metal and capacitor layers.Many of the circuits contained in this work are covered under patent protection in the United States and other countries. Some of the significant patent sources have been cited especially where the patent document was the only available source of publication known to the authors. The reader is urged not to assume that duplication here implies that any particular circuit is in the public domain.II. Current-Feedback AmplifiersThe concept of current-feedback dates to vacuum tube designs of the 1940s, and to early instrumentation amplifier design implemented with discrete transistors in the 1960s.These designs were mainly low gain-bandwidth, class-A implementations that did not provide the high slew rates that characterize todays current-feedback amplifiers. High slew rate can be achieved in some current-feedback designs since the amount of slew current can be made to be proportional to the input voltage. Traditional differential amplifiers have a fixed amount of bias current in the input-stage which sets a limit of the amount of current available for slewing. The 1980s brought the now familiar single-stage current-feedback amplifier where a level shift is performed using elementary Wilson current mirrors to inject the slew current to a compensation capacitor (Fig.3). While this topology is simple and works quite well, some phase margin is losr due to the propagation delay through the mirrors. Also, there is a tendency for the diode connected transistors used in the current mirror to self-saturate due to internal collector resistance while the amplifier attempts to provide peak slew current. While the single-stage current-feedback topology is very popular, acceptable open-loop transimpedance is not always high enough. One way to achieve higher open-loop transimpedance is to add another stage. However, stable biasing of the second-stage is a complex problem, and bandwidth is almost always scarificed.Perhaps the first publicly reported two-stage current-feedback amplifier is shown in Fig.4. By design, it lacked a dc current source style biasing to automatically set bias current in the second stage when the feedback loop was closed. Instead, the dc bias voltages were sensed and compared against a reference voltage. The difference was fed to a slow dc servo with high open-loop gain to force the bias point to stabilize. The open-loop transimpedance obtained was in excess of 2 M.III. Voltage-feedback AmplifiersIn the past decade, current-feedback has emerged as the dominant choice for high-speed amplifier designs; however, recently voltage-feedback has reemerged. Voltage-feedback offers several features that current-feedback does not, such as low noise at low gains, low level setting, the ablitily to design inverting integrators, etc. Applications such as active filters that require the ultimate in gain bandwidth and low noise can use, despite its advanced age, the single-stage folded-cascode design show in Fig.10.The p-n-p s are emitter followers or common bases only; consequently, they contribute at approximately ft only, and the small signal bandwidth of this amplifier is excellent.As with current-feedback, the ever-increasing speed of modern complementary bipolar processes can also be leveraged in voltage-feedback amplifier to obtain higher open-loop gain at more moderate frequencies to obtain higher open-loop gain at more moderate frequencies. These amplifier provide 14-to18-b linearity now demanded in the 500kHz to 20MHz signal range for signal processing applications. However, without doing some phase compensation, a good rule of thumb is that the potential bandwidth of the amplifier drops by factor of two for each added gain stageIV. Unity-Gain BuffersWhile both voltage and current-feedback amplifiers can be configured in gain of +1V/V, a unity-gain-only amplifier provides added flexibility. Typical applications, driving cables or flash converters, are unique in that maximum full power bandwidth is required plus the ability to drive large load capacitance. The chief advantage of this dedicated internally avoiding the delay through an external feedback network.To evaluate the relative performance of a dedicated buffer, three examples of typical 800MHz unity-gain buffers are compared. If the feedback was connected outside the package, a simplified total parasitic load model for a standard 8-pin SOIC style package might look like Fig.16.Fig.17 shows a simulation illustrating the three cases. Case 17(a) is the bandwidth plot where there are no parasitic; Case 17(b) is the bandwidth plot when the feedback is connected outside the package, on the package , on the circuit board; and case17(c) is the bandwidth plot with the feedback closed on-chip. Although 17(c) shows some peaking in the closed-loop response, it is clearly a great improvement over case 17(b) .A final method that is available to a unity-gain-only amplifier is to provide an open-loop output as shown in Fig.19. In this case , not only is the feedback connected on-chip, but the output capacitance is isolated from the feedback point by the beta of the drive transistors. The output resistance is not reduced by the loop gain any longer, although it is set by the bias current in the drive transistors and can be arbitrarily low. Also, the bandwidth is not a direct function of the load capacitance. Finally, the feedback loop keeps the offset relatively low.V. Distortion in bipolar amplifiersHarmonic and intermodulation distortion in amplifier has always been a concern to analog designers. Perhaps the best approach to low-distortion designers. Perhaps the best approach to low-distortion design is to address each distortion source separately. Also, despite the apparent differences ,the distortion mechanisms in voltage and current-feedback amplifiers are surprisingly similar.First, consider the output stage. Class-A output stages (Fig.20) do cause distortion despite some pseudo-science to the contrary, and the harmonics produced are both odd and even. Ignoring beta nonlinearity, then the equations for second and third harmonic distortion are, respectively:Each harmonic is at least a function of the input voltage (vin), the load resistance(RL), and the implied nominal power dissipation(IE). In fact, this is true of most distortion mechanisms. In most designs, the peak input voltage and load resistance are fixed, so as the quiescent current linearly decreases, the distortion exponentially increase.VI. Single-chip base array used to fabricate four amplifierWith this background in mind, a unique array of components has been fabricated on a common base chip. Consisting of transistors, resistors, and capacitors, the base array was used to produce a family of four state-of-the-art operational amplifiers with highly different characteristics. This approach was selected to maximize productivity of the design effort and to reduce development costs. This methodology required identifying the common elements in each devices architecture while adding the minimum of additional circuitry to form four distinct architectures.Each amplifier is optimized in some important area such as bandwidth, distortion, slew rate ,and power dissipation. An operational amplifier can be represented in block diagram form by the major elements shown in Fig.26. Each architecture uses all of these blocks as a way to share their commom elements, but all the blocks as a way to share their common elements, but the blocks are tailored to the requirements of the individual amplifiers. Table I shows the contrast between the important specifications of each amplifier architecture.A decision was made during the early phase of the project to choose a process that would enable the products to be distinguished on the basis of performance. Another compelling reason to emphasize performance was to offset the face that die size is not optimum due to the need to accommodate four different designs at one time. The AT&T CBIC-V2 process was chosen to achieve the desired performance. Table II shows a summary of the important features of this process.VII. Differential amplifier architecturesFig.27 through Fig.30 show simplified schematics of the four differential operational structures that have been implemented. The widest bandwidth architecture is the folded-casode and is shown in Fig.27. Being a single-stage amplifier, the dominant pole formed by output impedance of the gain stage and the compensation capacitor. Since there are a fewer secondary poles to deteriorate the phase margin than in a typical multi-stage amplifier, the bandwidth is maximized.Fig.28 shows a simplified schematic of the low-distortion amplifier; it has the highest open-loop gain and achieves lowest offset due to its balanced nature. Low, high-frequency distortion is achieved via a double integrator feedback loop applied around the second gain stage, thereby reducing the second-stage and output stage distortion mechanisms to second-order. The amplifier illustrated in Fig.29 is a current-feedback arrangement which axhieves the highest slew rate of the different configurations. This current-feedback amplifier has the property that bandwidth is normally independent of the gain, unlike voltage-feedback amplifiers where the bandwidth varies with the gain setting.The low-power amplifier shown in Fig.30 also uses the f