基于VHDL语言的电子秒表课题设计报告.doc

电子设计大赛课程设计报告 2010-2011学年第 二 学期教 学 单 位 信息工程与技术系 课 程 名 称 电子综合设计 年 级 专 业 08级电子信息工程 授 课 教 师 焦新涛 课题作者 梁彩云 一、 设计题目：基于VHDL语言的电子秒表设计（可调时，有闹钟、定时功能）二、 设计目的：掌握较复杂的逻辑设计和调试学习用原理图+VHDL语言设计逻辑电路学习数字电路模块层次设计掌握QuartusII软件及Modelsim软件的使用方法三、 设计内容：（一）设计要求1、 具有以二十四小时计时、显示、整点报时、时间设置和闹钟的功能。2、 设计精度要求为1S。（二）系统功能描述1 . 系统输入：系统状态及校时、定时转换的控制信号为k、set、ds； 时钟信号clk,采用实验箱的50MHz； 系统复位信号为reset。输入信号均由按键产生。系统输出：8位LED七段数码管显示输出，蜂鸣器声音信号输出。多功能数字钟系统功能的具体描述如下：2. 计时：set=1，ds=1工作状态下，每日按24h计时制计时并显示，蜂鸣器无声，逢整点报时。3. 校时：在set=0,ds=0状态下，按下“k键”，进入“小时”校准状态，之后按下“k键”则进入“分”校准状态，继续按下“k键”则进入“秒校准”状态，之后如此循环。1）“小时”校准状态：在“小时”校准状态下，显示“小时”数码管以1Hz的频率递增计数。2）“分”校准状态：在“分”校准状态下，显示“分”的数码管以1Hz的频率递增计数。3）“秒”复零状态：在“秒复零”状态下，显示“分”的数码管以1Hz的频率递增计数。4. 整点报时：蜂鸣器在“59”分钟的第5059，以1秒为间隔分别发出1000Hz，500Hz的声音。5. 显示：采用扫描显示方式驱动8个LED数码管显示小时、分、秒。闹钟：闹钟定时时间到，蜂鸣器发出交替周期为1s的1000Hz、500Hz的声音，持续时间为一分钟； 6. 闹钟定时设置:在set=0,ds=1状态下，按下“k”，进入闹钟的“时”设置状态，之后按下“k键”进入闹钟的“分”设置状态，继续按下“k 键”则进入“秒”设置状态, 之后如此循环。1） 闹钟“小时”设置状态：在闹钟“小时”设置状态下，显示“小时”的数码管以1Hz的频率递增计数。2） 闹钟：“分”设置状态：在闹钟“分”设置状态下，显示“分”的数码管以1Hz的频率递增计数。7. 定时器功能：在set=1,ds=0状态下，按下“k”，进入定时器的“时”设置状态，之后按下“k键”进入定时器的“分”设置状态，继续按下“k 键”则进入“秒”设置状态, 之后如此循环。在dsk=1时，定时器以1s为单位开始倒时，当dsk=0,停止倒时，在最后的十秒时间，蜂鸣器发出声音。(三)各功能模块设计说明及源程序1.1000Hz分频模块产生1000Hz频率2.1Hz模块产生1Hz频率3.计时，定时，闹钟，校时模块通过装换不同的状态，分别实现计时，定时，闹钟，校时功能；源程序如下4.顶层显示模块显示数码管，源代码如下：（四）.Modelsim综合仿真图四总结及体会通过这次电子设计大赛课程设计，我学到了很多，对于原本掌握的不好的数字逻辑相关知识，在课程设计具体实践中有了很深刻的认识，在对于Quartus+Modelsim仿真的操作上也有很大的提高，增加了操作的熟练程度。通过实验调试，我才真正地认识到了信号与变量的区别以及他们的使用方法。这份报告是用VHDL代码写的，比较长。相比之下，VERILOG语言显得简洁多了。不过可能是对VERILOG的学习还不够，调试中出现比较多的问题。故最后还是选择了VHDL语言的这份。最后，感谢在思维陷入困境时给予我指点，让我获得灵感的同学们！附录：各模块源程序1.1000Hz模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity frediv_1000 isport(clk : in std_logic;clkout : out std_logic );end frediv_1000;architecture rt3 of frediv_1000 isbeginprocess(clk)variable count:integer range 0 to 50000;beginif clkevent and clk = 1 thenif count = 49999 thencount := 0;elsecount := count + 1;if count = 24999 thenclkout = 1;elseclkout = 0;end if;end if;end if;end process;end rt3;2. 1HZ模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity frediv isport(clk : in std_logic;clkout : out std_logic );end frediv;architecture rt1 of frediv isbeginprocess(clk)variable count:integer range 0 to 50000000;beginif clkevent and clk = 1 thenif count = 49999999 thencount := 0;elsecount := count + 1;if count = 24999999 thenclkout = 1;elseclkout = 0;end if;end if;end if;end process;end rt1;3.计时，定时，闹钟，校时模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity adjust isport(rst,clk,k,set,alarm,ds,dsk : in std_logic;change_1,change_2 : in std_logic;fmo: out std_logic;sec,min,hour : out std_logic_vector(7 downto 0);end adjust;architecture rt1 of adjust issignal clk_1Hz,clk_1000Hz,clk_500Hz :std_logic;signal sec_r,min_r,hour_r :std_logic_vector(7 downto 0);signal sec_ra,min_ra,hour_ra :std_logic_vector(7 downto 0);signal sec_rd,min_rd,hour_rd :std_logic_vector(7 downto 0);signal fm_1:std_logic;signal cht,cmt,cst,cha,cma,csa,chd,cmd,csd :std_logic;signal sel_show:std_logic_vector(1 downto 0);type state_type is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11);signal state:state_type;component fredivport(clk : in std_logic;clkout : out std_logic );end component;component frediv_1000port(clk : in std_logic;clkout : out std_logic );end component;beginU1:frediv port map(clk,clk_1Hz);U3:frediv_1000 port map(clk,clk_1000Hz);-500Hzprocess(clk_1000Hz,rst)beginif (rising_edge(clk_1000Hz) thenif(rst = 0) thenclk_500Hz =0;elseclk_500Hz =not clk_500Hz;end if;end if;end process;process(clk)beginif sel_show(1 downto 0) = 11 then-shizhongsec = sec_r;min = min_r;hour = hour_r;else if sel_show(1 downto 0) = 01 then-naozhongsec = sec_ra;min = min_ra;hour = hour_ra;else if sel_show(1 downto 0) = 10 then-dingshisec = sec_rd;min = min_rd;hour = hour_rd;else if sel_show(1 downto 0) = 00 then-shizhongsec = sec_r;min = min_r;hour = hour_r;end if;end if;end if;end if;end process;process(clk_1Hz)beginif(rising_edge(clk_1Hz)thenif(rst=0)thenstate=s0;sel_show(1 downto 0)=11;cht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;else if (set = 1and ds=1)thensel_show(1 downto 0)=11;if(state=s4 or state=s5 or state=s6 or state=s7 or state=s8 or state=s9 or state=s10 or state=s11)thenstate=s0;else if( state=s0)thenif(k=0)thenstate=s1;else state=s0;end if;else if(state=s1)thencht=1;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;if(k=0)thenstate=s2;else state=s1;end if;else if(state=s2)thencht=0;cmt=1;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;if(k=0)thenstate=s3;else state=s2;end if;else if( state=s3 )thencht=0;cmt=0;cst=1;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;if(k=0)thenstate=s0;else state=s3;end if;end if;end if;end if;end if;end if;else if(set=0and ds=1)thensel_show(1 downto 0)=01;cht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;if(state=s0 or state=s1 or state=s2 or state=s3 or state=s8 or state=s9 or state=s10 or state=s11)thenstate=s4;else if( state=s4)thenif(k=0)thenstate=s5;elsestate=s4;end if;else if( state=s5)thencht=0;cmt=0;cst=0;cha=1;cma=0;csa=0;chd=0;cmd=0;csd=0;if(k=0)thenstate=s6;else state=s5;end if;else if(state=s6 )thencht=0;cmt=0;cst=0;cha=0;cma=1;csa=0;chd=0;cmd=0;csd=0;if(k=0)thenstate=s7;else state=s6;end if;else if(state=s7)thencht=0;cmt=0;cst=0;cha=0;cma=0;csa=1;chd=0;cmd=0;csd=0;if(k=0)thenstate=s4;else state=s7;end if;end if;end if;end if;end if;end if;else if(set=1and ds=0)thensel_show(1 downto 0)=10;cht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;if(state=s0 or state=s1 or state=s2 or state=s3 or state=s4 or state=s5 or state=s6 or state=s7)thenstate=s8;else if( state=s8)thenif(k=0)thenstate=s9;elsestate=s8;end if;else if( state=s9)thencht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=1;cmd=0;csd=0;if(k=0)thenstate=s10;else state=s9;end if;else if(state=s10 )thencht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=1;csd=0;if(k=0)thenstate=s11;else state=s10;end if;else if(state=s11)thencht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=1;if(k=0)thenstate=s8;else state=s11;end if;end if;end if;end if;end if;end if;elsesel_show(1 downto 0) = 00;cht=0;cmt=0;cst=0;cha=0;cma=0;csa=0;chd=0;cmd=0;csd=0;end if;end if;end if;end if;end if;end process;process(clk_1Hz)beginif clk_1Hzevent and clk_1Hz = 1 thenif rst = 0 thensec_r = 00000000;min_r = 00000000;hour_r = 9 thenmin_r(3 downto 0) = 5 thenmin_r(7 downto 4) = 0000;elsemin_r(7 downto 4) = min_r(7 downto 4) + 1;end if;elsemin_r(3 downto 0) = min_r(3 downto 0) + 1;end if;else if (change_2 = 0 and cmt = 1) thenif min_r(3 downto 0) = 0 thenmin_r(3 downto 0) = 1001;if min_r(7 downto 4) = 0 thenmin_r(7 downto 4) = 0101;elsemin_r(7 downto 4) = min_r(7 downto 4) - 1;end if;elsemin_r(3 downto 0) = min_r(3 downto 0) - 1;end if;else if (change_1 = 0 and cht = 1) thenif (hour_r(7 downto 4) = 2 and hour_r(3 downto 0) = 3 ) thenhour_r = 9)thenhour_r(3 downto 0) = 0000;hour_r(7 downto 4) = hour_r(7 downto 4) + 1;elsehour_r(3 downto 0) = hour_r(3 downto 0) + 1;end if;end if;else if (change_2 = 0 and cht = 1) thenif (hour_r(7 downto 4) = 0 and hour_r(3 downto 0) = 0 ) thenhour_r = 00100011;elseif(hour_r(3 downto 0) = 0 and hour_r(7 downto 4) 2)thenhour_r(3 downto 0) = 1001;hour_r(7 downto 4) = hour_r(7 downto 4) - 1;elsehour_r(3 downto 0) = 9 thensec_r(3 downto 0) = 5 thensec_r(7 downto 4) = 0000;elsesec_r(7 downto 4) = sec_r(7 downto 4) + 1;end if;elsesec_r(3 downto 0) = sec_r(3 downto 0) + 1;end if;else if (change_2 = 0 and cst = 1) thenif sec_r(3 downto 0) = 0 thensec_r(3 downto 0) = 1001;if sec_r(7 downto 4) = 0 thensec_r(7 downto 4) = 0101;elsesec_r(7 downto 4) = sec_r(7 downto 4) - 1;end if;elsesec_r(3 downto 0) = 9 thensec_r(3 downto 0) = 5 thensec_r(7 downto 4) = 9 thenmin_r(3 downto 0) = 5 thenmin_r(7 downto 4) = 0000;if hour_r(7 downto 4) = 2 thenif hour_r(3 downto 0) = 3 thenhour_r = 00000000;else hour_r(3 downto 0) = 9)thenhour_r(3 downto 0) = 0000;hour_r(7 downto 4) = hour_r(7 downto 4) + 1;else hour_r(3 downto 0) = hour_r(3 downto 0) + 1;end if;end if;elsemin_r(7 downto 4) = min_r(7 downto 4) + 1;end if;elsemin_r(3 downto 0) = min_r(3 downto 0) + 1;end if;elsesec_r(7 downto 4) = sec_r(7 downto 4) + 1;end if;elsesec_r(3 downto 0) = sec_r(3 downto 0) + 1;end if;end if;end if;end if;end if;end if;end if;end if;end if;end process;process(clk_1Hz)beginif clk_1Hzevent and clk_1Hz = 1 thenif rst = 0 thensec_ra = 00000000;min_ra = 00000000;hour_ra= 9 thenmin_ra(3 downto 0) = 5 thenmin_ra(7 downto 4) = 0000;elsemin_ra(7 downto 4) = min_ra(7 downto 4) + 1;end if;elsemin_ra(3 downto 0) = min_ra(3 downto 0) + 1;end if;else if (change_2 = 0 and cma = 1) thenif min_ra(3 downto 0) = 0 thenmin_ra(3 downto 0) = 1001;if min_ra(7 downto 4) = 0 thenmin_ra(7 downto 4) = 0101;elsemin_ra(7 downto 4) = min_ra(7 downto 4) - 1;end if;elsemin_ra(3 downto 0) = min_ra(3 downto 0) - 1;end if;else if (change_1 = 0 and cha = 1) thenif (hour_ra(7 downto 4) = 2 and hour_ra(3 downto 0) = 3 ) thenhour_ra = 9)thenhour_ra(3 downto 0) = 0000;hour_ra(7 downto 4) = hour_ra(7 downto 4) + 1;elsehour_ra(3 downto 0) = hour_ra(3 downto 0) + 1;end if;end if;else if (change_2 = 0 and cha = 1) thenif (hour_ra(7 downto 4) = 0 and hour_ra(3 downto 0) = 0 ) thenhour_ra = 00100011;elseif(hour_ra(3 downto 0) = 0 and hour_ra(7 downto 4) 2)thenhour_ra(3 downto 0) = 1001;hour_ra(7 downto 4) = hour_ra(7 downto 4) - 1;elsehour_ra(3 downto 0) = 9 thensec_ra(3 downto 0) = 5 thensec_ra(7 downto 4) = 0000;elsesec_ra(7 downto 4) = sec_ra(7 downto 4) + 1;end if;elsesec_ra(3 downto 0) = sec_ra(3 downto 0) + 1;end if;else if (change_2 = 0 and csa = 1) thenif sec_ra(3 downto 0) = 0 thensec_ra(3 downto 0) = 1001;if sec_ra(7 downto 4) = 0 thensec_ra(7 downto 4) = 0101;elsesec_ra(7 downto 4) = sec_ra(7 downto 4) - 1;end if;elsesec_ra(3 downto 0) = sec_ra(3 downto 0) - 1;end if;end if;end if;end if;end if;end if;end if;end if;end if;end process;process(clk_1Hz)beginif clk_1Hzevent and clk_1Hz = 1 thenif rst = 0 thensec_rd = 00000000;min_rd = 00000000;hour_rd = 9 thenmin_rd(3 downto 0) = 5 thenmin_rd(7 downto 4) = 0000;elsemin_rd(7 downto 4) = min_rd(7 downto 4) + 1;end if;elsemin_rd(3 downto 0) = min_rd(3 downto 0) + 1;end if;else if (change_2 = 0 and cmd = 1) thenif min_rd(3 downto 0) = 0 thenmin_rd(3 downto 0) = 1001;if min_rd(7 downto 4) = 0 thenmin_rd(7 downto 4) = 0101;elsemin_rd(7 downto 4) = min_rd(7 downto 4) - 1;end if;elsemin_rd(3 downto 0) = min_rd(3 downto 0) - 1;end if;else if (change_1 = 0 and chd = 1) thenif (hour_rd(7 downto 4) = 2 and hour_rd(3 downto 0) = 3 ) thenhour_rd = 9)thenhour_rd(3 downto 0) = 0000;hour_rd(7 downto 4) = hour_rd(7 downto 4) + 1;elsehour_rd(3 downto 0) = hour_rd(3 downto 0) + 1;end if;end if;else if (change_2 = 0 and chd = 1) thenif (hour_rd(7 downto 4) = 0 and hour_rd(3 downto 0) = 0 ) thenhour_rd = 00100011;elseif(hour_rd(3 downto 0) = 0 and hour_rd(7 downto 4) 2)thenhour_rd(3 downto 0) = 1001;hour_rd(7 downto 4) = hour_rd(7 downto 4) - 1;elsehour_rd(3 downto 0) = 9 thensec_rd(3 downto 0) = 5 thensec_rd(7 downto 4) = 0000;elsesec_rd(7 downto 4) = sec_rd(7 downto 4) + 1;end if;elsesec_rd(3 downto 0) = sec_rd(3 downto 0) + 1;end if;else if (change_2 = 0 and csd = 1) thenif sec_rd(3 downto 0) = 0 thensec_rd(3 downto 0) = 1001;if sec_rd(7 downto 4) = 0 thensec_rd(7 downto 4) = 0101;elsesec_rd(7 downto 4) = sec_rd(7 downto 4) - 1;end if;elsesec_rd(3 downto 0) = sec_rd(3 downto 0) - 1;end if;else if dsk=0 thenif sec_rd(3 downto 0) = 0 thensec_rd(3 downto 0) = 1001;if sec_rd(7 downto 4) = 0 thensec_rd(7 downto 4) = 0101;if min_rd(3 downto 0) = 0 thenmin_rd(3 downto 0) = 1001;if min_rd(7 downto 4) = 0 thenmin_rd(7 downto 4) = 0101;if hour_rd(7 downto 4) = 0 thenif hour_rd(3 downto 0) = 0 thenhour_rd = 00100011;else hour_rd(3 downto 0) = hour_rd(3 downto 0) - 1;end if;elseif(hour_rd(3 downto 0) = 0)thenhour_rd(3 downto 0) = 1001;hour_rd(7 downto 4) = hour_rd(7 downto 4) - 1;else hour_rd(3 downto 0) = hour_rd(3 downto 0) - 1;end if;end if;elsemin_rd(7 downto 4) = min_rd(7 downto 4) - 1;end if;elsemin_rd(3 d