CDCintroductionv2.ppt

cdcintroductionfeintteamlillianwei june16 2011 outline cdcintroduction cdcbasicconceptfeintcdcoverviewfeintcdcdebugtileflowfullchipflowsuggestionforfutureproject cdcintroduction 3 cdcbasicconcept overview cdcintroduction whatiscdc cdc clockdomaincrossing itisdefinedasaflop to floppathwheretransmittingflopistriggeredbyaclockthatisasynchronoustothereceivingflopclock overview cdcintroduction overview cdcintroduction metastability overview cdcintroduction howtoprotectagainstthepost siliconfailuresproducedbycdc designersshouldtakecdcissuesseriouslyandusevalidcdcschemeinhardwaredesignstage efficientverificationschemeshouldbeusedtodoublecheckcdcholesindesign ourjob spyglasscdcbyatrenta before9xx 0incdcbymentor cdcintroduction 8 feintcdcoverview feintcdcoverview cdcintroduction aswehavelec cdclifeiseasier what smore designperiodisshorter feintcdcoverview tilelevelflow cdcintroduction 10 cdcintroduction 11 feintcdcoverview tilelevelflow setup tcltemplate tcltemplatezin3 tclgenerate tclprocs tcl guts40incdc vf file projectfilesproject tclconfig tcl usercustomization toolrunscript rpts logs hierctrlfile userinputs projectinputs gutsinfrastructure outputs libraries rtlfiles 0intool tile run bsub tile run tile run tcl feintcdcoverview tilelevelflow cdcintroduction 12 feintcdcoverview chiplevel cdcintroduction 13 chip io core chip pad tile feintcdcoverview chiplevel cdcintroduction 14 ifthereisnoinfoforthepadthen0inwillreportablackboxcrossingdefaultfortheflowtogenerateandusecontrolfilesforallpads butthiscausesnoiseintherunschangingtoauserdefinedlistinthefuture chip core io tile pad macro feintcdcoverview chiplevelflow cdcintroduction 15 cdcintroduction 16 feintcdcdebug debugsteps resolveinferredclockscleanwarningscleanviolations gutsnewusertraining 17 step1 resolveinferredclocks tile chip lookinto cdcwrkdir tile cdc output 0in cdc design rpt search inferredclockgroups ifthenumisnot0 refinetheclockdefinationinctrlfileandreruncdctillnoinferredclk clockgroupsummaryfor ds t totalnumberofclockgroups 3numberofuser definedclockgroups 3numberofinferredclockgroups 0numberofignoredclockgroups 0 cdcintroduction 18 step2 cleanimportantwarnings tile lookinto cdcwrkdir tile cdc output 0in detail log searchbelowwarningsandcleanthem warning netlist 44incompleteinput outputspecificationsfortheblocksinsidetopmodule warning netlist 78tileinputportisunusedwarning netlist 79tileoutputportisundrivenwarning netlist 80tileportclockdomaincannotbeinferred weshouldexpect0netlist 80warningtogenerategoodhiercontrolfile cdcintroduction 19 moreinfo http sharedbook twiki bin view capeverde tilelevelcdc warning review update warning netlist 44incompleteinput outputspecificationsfortheblocksinsidetopmodule cdcintroduction 20 sub block dff topmodule theoutputportofthesub blockisnotdefined toolwillskipthecdccheckforit clk a step2 cleanimportantwarnings tile step2 cleanimportantwarnings tile warning netlist 78tileinputportisunusedinputportofahierarchicalcdcblockisnotusedbytheblock portismarkedwiththe ignoreflaginthecfm checkthattheportistrulyunused cases reallyunusedintentlyorreservedforlaterstep scanlogic seemsused butreallynotusedforspeciallogic mux and cdcintroduction 21 step2 cleanimportantwarnings tile warning netlist 79tileoutputportisundriven outputportofahierarchicalcdcblockisnotdrivenintheblock portismarkedwiththe ignoreflaginthecfm checkthattheportistrulyundriven iftheportshouldbepartofaclockdomain addaset cdc port domaindirectivefortheporttothehierarchicalconstraintsfilefortheblock case 1 reallyundriven coveredindesignproblem waiver 2 drivenbyencryptmodule cdcintroduction 22 step2 cleanimportantwarnings tile warning netlist 80tileports clockdomaincannotbeinferred thiswarningisissuedforaninputportiftheportfansouttooutputportsusingcombinationallogic notsequentiallogic ifyouspecifythe combo pathoptiontotheset cdc port domaindirectivesfortheoutputportsandtheinputportsarelisted thenyoucanignorethismessage cdcintroduction 23 step2 cleanimportantwarnings chip cdcintroduction 24 warning netlist 44incompleteinput outputspecificationsforport warning netlist 56tileclockconstraintviolated warning netlist 58tileportnotdefinedasaclockinblockcontrolfile warning netlist 61tileclocknotconnectedtoaclockattoplevel belowtwotypesarenotfoundinverde warning netlist 60blockportisnotaconstant warning netlist 70inconsistentconstantvaluesatblockandtoplevel moreinfo step3 cleanimportantviolations tile mostcommonviolationtypes 1 no sync2 multi bits3 combo logic4 redundant5 black box whichneedtowaive whichneedtofix cdcintroduction 25 tileviolationdebug no sync single bitsignaldoesnothavepropersynchronizer cdcintroduction 26 tileviolationdebug violationexample no sync cdcintroduction 27 no sync clkp1500 tclk fromvl sms bf t sms proc sms 1 stp u bf t sms proc ieee1500 sms si clksclk tovl sms bf t sms proc sms 1 stp u bf t sms proc ctrl status r 0 id no sync 91489 tileviolationdebug multi bits multiple bitsignalacrossclockdomainboundary cdcintroduction 28 tileviolationdebug violationexample multi bits cdcintroduction 29 multi bits clkp1500 tclk fromvl sms ds t sms proc sms 1 stp u ds t sms proc ieee1500 wir r clksclk tovl sms ds t sms proc sms 1 stp u ds t sms proc met m instr id multi bits 494 tileviolationdebug combo logic combinationallogicbeforesynchronizer cdcintroduction 30 tileviolationdebug violationexample combinationallogicbeforesynchronizer cdcintroduction 31 combo logic clksclk frompgfsm pgfsm cntl reg 6 clkdclk touvdm uvdm core uvd rst sync rst combine dclk sync hard sync r d id combo logic 24638 tileviolationdebug redundant redundantsynchronization cdcintroduction 32 tileviolationdebug violationexample redundant cdcintroduction 33 tileviolationdebug blackbox crossingdrivesaninstanceofaninferredblackbox cdcintroduction 34 tileviolationdebug violationexample blackbox cdcintroduction 35 note forblackboxviolations agoodwaytofixissetblack boxforthesub block andsetportdomainfortheioportsofthesub blockiftheyneedtocheckcdc blackbox clksclk fromtmonw0 thm tmon tmon bgadj ff 2 clk totmonw0 utmons utmon tmon bgadj2 id blackbox 18164 tileviolationdebug casesofclockn aintheviolationrpt tileprimaryinputport a connectedtodifferentclockdomainregisters tilelevelmisscrossingcheck cdcintroduction 36 tileviolationdebug b definedas async inthectrlfile defaultisnotasync see tile cdc output 0in detail log globalcdcpreference optionvalue input asyncfalseifneedchangeit set 0inset cdc preference input async cdcintroduction 37 tileviolationdebug 2 frombbox soutput 3 connecttothe d pinofasynccell duetodefine asyncforthesynccell sdpin cdcintroduction 38 step3 cleanimportantviolations chip mostcommonviolationtypes 1 black box2 combo logic3 multi bits4 no sync cdcintroduction 39 chipviolationdebug violationexample blackbox cdcintroduction 40 note forblackboxviolations indeeditisatoolbug asallmodulesiscfmmodelorbeensetasblackbox sonoblackboxissueisexpected heretheblackboxviolationsareallgoodcrossing waived johnwortman reason theseareokeytowaivesincethereisthesynccellintherecieverside date 03 03 2011 comments goodcrossing toolissue cdc0inwaivejohnwchipblackboxclksclk fromcore ct t smu mc misc vbi clkmclk tocore mcd t 0 1 smu mc misc vbi 0inset cdc port domainsmu mc misc vbi clockcg tile gbl sclk modulect t 0inset cdc port domainsmu mc misc vbi async clockio mcd chp mclk src modulemcd t violation blackbox clksclk fromcore ct t smu mc misc vbi clkmclk tocore mcd t0 smu mc misc vbi chipviolationdebug violationexample combo logic cdcintroduction 41 combo logic clk fromcore ct t smu sq power throttle cycle incr clksclk tocore sqc 000 smu sq power throttle cycle incr id combo logic 66295 hierctrlfile 0inset cdc port domainsmu sq power throttle cycle incr clockcg tile gbl sclk combo pathio targ io resetbio cg xtalin clkbif cg bclk srccts delay cselcts delay cbypasscg tile gbl sclk modulect t combo logic 0inset cdc port domainsmu sq power throttle cycle incr async clockcg gbl sclk modulesqc0 t chipviolationdebug violationexample combo logic cdcintroduction 42 chipviolationdebug violationexample combo logic cdcintroduction 43 waived mihirdoctor reason noglitchonthecombo logic date 03 06 2011 comments althoughtheendpointissyncedtosclkdomain thestartpoint fromct ttile isfanedoutfromcombo logic andthecombo logic sinputisfromdifferentclockdomains sclk bclk xclk sowecouldseeacombo logicissueintherpt mihir thisisfinetowaive muxesyoushoweddonotswitchdynamically wesetthemonceatbootupanddonotchangeafterwards cdc0inwaiveliweichipcombo logicclk fromcore ct t smu sq power throttle cycle incr clksclk tocore sqc 0 00 01 10 11 smu sq power throttle cycle incr note suggestiononsuchcaseisflip flopouteachprimaryoutputforalltiles chipviolationdebug violationexample multi bits cdcintroduction 44 multi bits clk fromcore cpl efuse t io rcu efuse0 q clkzclk tocore ct t io rcu efuse0 q id multi bits 85164 hierctrlfile 0inset cdc port domainio rcu efuse0 q clocksmu clk clk mon divide d0nt sdc set false path to zclk y modulect t 0inset cdc clocksmu clk clk mon divide d0nt sdc set false path to zclk y modulect t virtual groupzclk waived jeffreyzhang reason theio rcu efuse0 issemi static programedonceandneverchange sosurelynotletthedestinationflopgoingmetastable date 02 11 2011 comments clkisbecausenodefinationforportsofcpl efuse t smacroefuse 128x32 ls ovlb1 cdc0inwaivejefzhangchipmulti bitsclk fromcore cpl efuse t io rcu efuse0 q clkzclk tocore ct t io rcu efuse0 q chipviolationdebug violationexample multi bits cdcintroduction 45 chipviolationdebug violationexample no sync cdcintroduction 46 no sync clksclk fromcore gdc t rcu gdc bif cec hard resetb clk tocore bf t rcu gdc bif cec hard resetb id no sync 70046 hierctrlfile 0inset cdc port domainrcu bif cec hard resetb clockcg tile gbl sclk modulect t combo logic 0inset cdc port domainrcu gdc bif cec hard resetb combo pathrcu bif cec hard resetb modulegdc t 0inset cdc port domainrcu gdc bif cec hard resetb nosync modulebf t combo logic chipviolationdebug violationexample no sync cdcintroduction 47 0inset cdc port domainrcu bif cec hard resetb clockcg tile gbl sclk modulect t combo logicct t rcu reset v wirepre rcu cec chip resetb scan mode io resetb dglitch rstb chipviolationdebug violationexample no sync cdcintroduction 48 0inset cdc port domainrcu gdc bif cec hard resetb nosync modulebf t combo logic waived aqin reason theseincomingsignalsaresynchronizedbeforeuse date 04 13 2011 comments isbecausercu gdc bif cec hard resetbgoestobothsynccellanddebugbuswithcombologic duetotoollimitation hideacombo logicissuehere rcu bif cec hard resetbgoesoutfromct twithcombo logic throughgdc t thenfeedintobf t vineyconfirmedit sglitchfreeoutofct t seemail2011 04 15 sosafetowaive ct t rcu reset v wirepre rcu cec chip resetb scan mode io resetb dglitch rstbcdc0inwaiveaqinchipno syncclksclk fromcore gdc t rcu gdc bif cec hard resetb clk tocore bf t rcu gdc bif cec hard resetb chipviolationdebug violationexample no sync cdcintroduction 49 cdcintroduction 50 tilelevelcdcflow tilelevelcdcflow willcover prepareinputfiles howtorun whathavebeendoneintherun flowoutputfiles cdcintroduction 51 tilelevelcdcflow prepareinputfiles howtorun whathavebeendoneintherun flowoutputfiles cdcintroduction 52 tilelevelcdcflow flowinputfiles 1 rtlcode generatedby runtileflow csh t tile stepsms stem main auto verde amd64rh3 0 dbg src tiles tile tile sms rtl cdcintroduction 53 tilelevelcdcflow flowinputfiles 2 sdcfile generatedby runtileflow csh t tile stepgensdc4cdc stem main nl wrk variant verde tile sdc cdc tile sdcthesdcfileisusedasastartingpointfortheconstraints cdcintroduction 54 tilelevelcdcflow flowinputfiles 3 ctrlfiles manuallytyped setsomeconstraintsforcdcanalysis justlikeclockgroupoftheclockorport blackbox customsynccell morelater global stem main cmn tools guts variant verde project 0in ctrl vtilelevel stem main nl setup variant verde tile tile tile 0in ctrl vbasectrlfile provide maintainbycadteam stem main cmn tools guts bin cdc0in guts0incdc base ctrl v cdcintroduction 55 tilelevelcdcflow prepareinputfiles howtorun whathavebeendoneintherun flowoutputfiles cdcintroduction 56 tilelevelcdcflow howtorun runtileflow csh t tile stepcdc0in callguts40incdcscript gen tile run tcl include0inruncmd cdcintroduction 57 tilelevelcdcflow configtoolversion 0in 3 0c p1 cdcintroduction 58 thisvariableisseteachtimeopeninganewshell stem main setup scripts init modules fe versions variant project default 0insetenvgpg 0in version3 0c p1 tilelevelcdcflow thengpg 0in versionisusedin stem cmn tools guts variant project config tcl if target cdc0in setconfig toolversion 0in env gpg 0in version regexp 0in d config toolversion matchcdcversionif cdcversion 2 setconfig templatescr config toolroot cdc0in template tcl elseif cdcversion 3 setconfig templatescr config toolroot cdc0in templatezin3 tcl note donotuse moduleload tochoosetoolversion whatreallyusedby0inflowisdecideby toolversion cdcintroduction 59 tilelevelcdcflow cdcintroduction 60 0incdc report settings d tile hier ctrl stem main cmn tools guts bin cdc0in guts0incdc base ctrl v ctrl stem main cmn tools guts variant verde project 0in ctrl v ctrl stem main nl setup variant verde tile tile tile 0in ctrl v formal formal effortlow process dead end sdc in stem main nl wrk variant verde tile sdc cdc tile sdc 0inruncmd tilelevelcdcflow prepareinputfiles howtorun whathavebeendoneintherun flowoutputfiles cdcintroduction 61 tilelevelcdcflow whathavebeendoneintherun cdcintroduction 62 worksonrtlsourcecode analysisthedesignautomaticallyidentifiesallclocksandclockdomaincrossingsautomaticallyidentifiescorrect incorrectandmissingsynchronizersprovidesaneasy to usedebug analysisenvironment tilelevelcdcflow analysissteps step1 extract0insettingsfromconfigfilesandctrlfilestosetbasicrunenv eg toolversion sourcertlcode rtlsearchpath libaray debugflags 0in debug blackbox empty module fix verilog redecl port cdc hier fix ports not gen cdc allow top port ignore cdc skip dmux 0in licq v26 hier report any clockoutputfilelocation andothersettingslikebbox constant validsynccell clockgroups inctrlfile cdcintroduction 63 tilelevelcdcflow analysissteps step2 generatetheclockgroupreport 0in cdc design rpt eg clockgroupsummaryfor module totalnumberofclockgroups 2numberofuser definedclockgroups 2numberofinferredclockgroups 0numberofignoredclockgroups 0 cdcintroduction 64 tilelevelcdcflow analysissteps user specifiedclockgroups group0 sclk 68828registerbits cg gbl sclk group1 p1500 tclk 879registerbits tst targ p1500 tclk cdcintroduction 65 tilelevelcdcflow analysissteps step3 modifyclockconstraintsifthereareanyincorrectclocks somecasesofinferredclocks inferredclockbecausemuxselpinnottiehigh low aviodbysetconstantlike 0inset constantmodule mux sel1 b0inferredclockbecauseotherreasonlikeclockcouldnotpropagate eg clkthrupdlycell avioldbysettingclockgrouplike 0inset cdc clockmcd ch0 mclk ctrl mrk pdlycell mclk tx d0nt pdlyhc8f0v0 z groupmclkinferredclockwhichdon tneedcare avioldbysettingclockwith ignore 0inset cdc clocktest clk ignore cdcintroduction 66 tilelevelcdcflow analysissteps basicrulesofgeneratedirectivesforclocks primaryinputclocksignalsaretheirowndomain gated dividedclocksareusuallygroupedwiththesourceclockdomain multiplexedclocksdefineanewdomain forinputdoesnotbelongtoanyclockdomain shouldsetlikebelow 0inset cdc port domaininput signal async cdcintroduction 67 tilelevelcdcflow analysissteps thespecifiedclockmustexistwithinthedesignorbedefinedasavirtualclock 0inset cdc clockclka virtual 0inset cdc port domainsiga clockclka cdcintroduction 68 tilelevelcdcflow analysissteps step4 performcdcchecks iftheclockgroupsandi oportdomainsareallsetcorrectly thenthetoolperformcompletecdccheck thecheckingisexhaustiveoneachcdcpath finallygettwoimportantfiles theviolationreportfile 0in cdc rpt guidebugdatabase 0in cdc db cdcintroduction 69 tilelevelcdcflow analysissteps cdcintroduction 70 theviolationreportfile 0in cdc rpt cdcsummary violations 866 single bitsignaldoesnothavepropersynchronizer 103 combinationallogicbeforesynchronizer 18 multiple bitsignalacrossclockdomainboundary 184 redundantsynchronization 6 blackboxcrossing 535 tilelevelcdcflow analysissteps cdcintroduction 71 theviolationreportfile 0in cdc rpt tclk start tst targ p1500 trstb ct t v 808 zclk end smu rcu nfl rcu io efuse0 csb ct t nfl v 84 id no sync 99878 via p1500 tile tst targ p1500 trstbvia p1500 tile p1500 wrstn via smu rcu nfl nfl resetb tilelevelcdcflow analysissteps cdcintroduction 72 step5 debug resolveviolationscheckwiththeviolationsin0in cdc rpt usetheschemeidtoloadtheviolatedpathingui toseeiftheviolationsisarealone ifyes fixinrtl elseaddwaiver cdcdebug cdcintroduction 73 thousandsofviolations firstlycleanglobalissues gfxtilesaregoodcandidatesbecausetheyonlyhaveoneclockdomain secondlygrouptheviolationsbydifferentscheme third foreachscheme groupviolationsbytheviolatedpaths startpointorendpoint 4 detaildebugusinggui cdcdebug startgui useguitodebug cdcintroduction 74 setenvtilexxx bin tcsh feval modulecmdtcshload0in 3 0c p1 setnum grepbsub tile run bsub awk f tile print 2 awk print 1 bsub is qnormal pverde impl jguts cdc0in tile num r select type rhel4 64 type rhel5 64 gb32 gb64 gb128 csbatch rusage mem 5000 duration 2h swp 10000 span hosts 1 0in cdc0in cdc db scriptofstartgui cdcdebug startgui startedgui cdcintroduction 75 cdcdebug startgui differentseverityofrunresult cdcintroduction 76 by 0inset cdc report severitywaived onlyshowinguiwhenthisdirectiveison 0inset cdc preference filtered report metastablevaluesarealwaysblocked ifpossiable needtousesimulationdoprotocolverification 1 single multibitsignalwithoutasynchronizer 2 combinationallogicattheinputofasynchronizer3 reconvergenceofsynchronizersneedmorepain cdcdebug waiverfiles therearetwokindsofwaiver internal addwaiverdirectivesin tile 0in ctrl v eg 0inset cdc report touvdm uvdm core cgc blk busy sync sync r sync r severitywaived promotionoff comment author omar logicwillnotglitchbydesign thereisafilterthatwillremoveglitches external tile wa