DDR SDRAM基础知识.pptx

DRAMBasicKnowledgeSummary HulinCao caohulin 1 DRAMBasicKnowledge DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureAddressMappinginDRAMController 2 DRAMBasicKnowledge DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureAddressMappinginDRAMController 3 DRAMDeviceArchitecture TypicalDRAMDeviceArchitectureSimple 1T 1CDatalosseswhenreadorover time 4 DRAMDeviceArchitecture DataWidthofDRAMDeviceAlsothedatawidthofeachbankEachDRAMdevicewillhaveseveralbanks Cont d 5 DRAMDeviceArchitecture Bank Rank Channel Cont d 6 DRAMDeviceArchitecture Bank Cont d 7 DRAMDeviceArchitecture Rank Cont d 8 DRAMDeviceArchitecture Channel Cont d 9 DRAMDeviceArchitecture OverviewofBank Rank Channel Cont d 10 DRAMDeviceArchitecture Example TransferaCacheBlock Cont d 0 xFFFF F 0 x00 0 x40 64Bcacheblock Physicalmemoryspace Channel0 DIMM0 Rank0 Mappedto 11 DRAMDeviceArchitecture Example TransferaCacheBlock Cont d 0 xFFFF F 0 x00 0 x40 64Bcacheblock Physicalmemoryspace Rank0 Chip0 Chip1 Chip7 Data 8B Row0Col0 8B 12 DRAMDeviceArchitecture Example TransferaCacheBlock Cont d 0 xFFFF F 0 x00 0 x40 64Bcacheblock Physicalmemoryspace Data 8B 8B 8B Rank0 Chip0 Chip1 Chip7 Row0Col1 13 DRAMDeviceArchitecture Example TransferaCacheBlock Cont d 0 xFFFF F 0 x00 0 x40 64Bcacheblock Physicalmemoryspace Data 8B 8B Rank0 Chip0 Chip1 Chip7 Row0Col1 A64Bcacheblocktakes8I Ocyclestotransfer Duringtheprocess 8columnsarereadsequentially 14 DRAMBasicKnowledge DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureAddressMappinginDRAMController 15 DRAMAccessFlow DRAMAccessFlowOverview 16 DRAMAccessFlow DifferentialSenseAmplifier RowBuffer Cont d 17 DRAMAccessFlow CircuitsofDifferentialSenseAmplifier Cont d 18 DRAMAccessFlow ReadAccessStep1 WordLineSelect Cont d 19 DRAMAccessFlow ReadAccessStep2 SenseAmplifier Cont d 20 DRAMAccessFlow ReadAccessStep3 Restore Cont d 21 DRAMAccessFlow ReadAccessStep4 Pre charge Cont d 22 DRAMAccessFlow SenseAmplifierVoltageWaveform ReadFlow Cont d 23 DRAMAccessFlow WriteAccessFlow Cont d 24 DRAMBasicKnowledge DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommands TimingParametersDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureAddressMappinginDRAMController 25 DRAMBasicCommands KeyTimingParameters 26 DRAMBasicCommands RowAccessCommand Activation Cont d 27 DRAMBasicCommands ColumnReadCommand Cont d 28 DRAMBasicCommands ColumnWriteCommand Cont d 29 DRAMBasicCommands PrechargeCommand Cont d 30 DRAMBasicCommands RefreshCommand Cont d 31 DRAMBasicCommands MoreaboutDRAMRefreshThememorycontrollerneedstorefresheachrowperiodicallytorestorechargeReadandcloseeachroweveryNmsTypicalN 64msDownsideofDRAMRefreshPowerConsumePerformancedegradationRefreshratelimitsDRAMcapacityscaling Cont d 32 DRAMBasicCommands MoreaboutDRAMRefreshRefreshMethodBurstrefreshDistributedrefresh Cont d 33 DRAMBasicCommands MoreaboutDRAMRefresh Cont d 34 DRAMBasicCommands MoreaboutDRAMRefresh Cont d 35 DRAMBasicCommands DRAMRefreshinLPDDRxTCSRTemperatureCompensatedSelfRefreshEmbeddedtemperaturesensor adjustrefreshperiodbasedontemperature AlsoAdoptedinDDR4 PASRPartialArraySelfRefreshOnlyusepartoftheDRAMtosavepower Cont d 36 DRAMBasicCommands AReadCycle Cont d 37 DRAMBasicCommands PowerConsumeinDRAMReadCycle Cont d 38 DRAMBasicCommands PowerRelatedTimingParameters tRRDtRRD RowtoRowactivationDelay differentbankWillaffectDRAMcommandscheduling Cont d 39 DRAMBasicCommands PowerRelatedTimingParameters tFAWtFAW FourBankActivationWindowWillaffectDRAMcommandscheduling Cont d 40 DRAMBasicCommands ThevalueoftRRDandtFAWisPageSizeRelatedExample 1GbitDDR2SDRAMdevicefromMicron Cont d 41 DRAMBasicCommands TheTrendoftRRDandtFAW Cont d 42 DRAMBasicCommands tRRDandtFAWinDDR4 Cont d 43 DRAMBasicKnowledge DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageHit MissPageOpen ClosePolicyBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureAddressMappinginDRAMController 44 DRAMCommandSchedule Page RowBuffer Hit MissPageHitNextRead WriteAccessisinthesamebank samerowAccessFlow Read WriteCommand DataTransactionPageMissNextRead WriteAccessisinthesamebank differentrowAccessFlow Prechargetothecurrentrow Activenextrow Read WriteCommand DataTransaction Cont d 45 DRAMCommandSchedule Page RowBuffer Hit MissDemo Cont d RowBuffer Row0 Column0 Rowdecoder Columnmux Rowaddress0 Columnaddress0 Data Row0 Empty Row0 Column1 Columnaddress1 Row0 Column85 Columnaddress85 Row1 Column0 HIT HIT Rowaddress1 Row1 Columnaddress0 CONFLICT Columns Rows AccessAddress 46 DRAMCommandSchedule PageOpenKeeptherowopenafteranaccessNextaccessmightneedthesamerow rowhitNextaccessmightneedadifferentrow rowconflict wastedenergyPageCloseClosetherowafteranaccess ifnootherrequestsalreadyintherequestbufferneedthesamerow Nextaccessmightneedadifferentrow avoidarowconflictNextaccessmightneedthesamerow extraactivatelatency Cont d 47 DRAMCommandSchedule BankInterleaveLowtimecostwhenswitchbetweendifferentbankUsecertainaddressmappingtoincreasebankinterleaveAddressMappingExample Row Bank ColumnCommandReorderReorderDRAMcommandstoimplementbankinterleaveandincreasepagehitrateReorderreadandwriteaccesscommandsGivereadcommandahigherpriorityReorderread writecommandqueuetoincreasepagehitrate bankinterleave Cont d 48 DRAMCommandSchedule ExampleofBankInterleaveandCommandReorder Cont d 49 DRAMCommandSchedule PerformanceAnalyzeofSchedulePolicyPerformanceTestScenarioDual Core DDR266 4ranksperchannelWeb Serverbenchmark Figure1 Read Write 2 1 RandomAddress Figure2 3 SchedulePolicyMC A0 Page Open NoBank RankInterleave In OrderMC A1 MC AwithRankInterleaveMC A2 MC AwithBankInterleaveandPage CloseMC B0 Page Close Bank RankInterleave In OrderMC B1 MC B0withRe Order givereadcommandhigherprioritybutread writecommandqueueinorderMC B2 MC B1withRe OrderinRead WriteCommandQueueNote Theordermeanstheorderofread writeaccess Cont d 50 DRAMCommandSchedule PerformanceAnalyzeofSchedulePolicy Cont d Web Serverbenchmark 51 DRAMCommandSchedule PerformanceAnalyzeofSchedulePolicy Cont d Read Write 2 1RandomAddress 52 DRAMCommandSchedule PerformanceAnalyzeofSchedulePolicy Cont d Read Write 2 1RandomAddress 53 Part1 DRAMBasicKnowledge DRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageHit MissPageOpen ClosePolicyBankInterleaveCommandsRe OrderDRAMControllerBasicDRAMControllerFunction ArchitectureAddressMappinginDRAMController 54 DRAMControllerBasic FunctionofDRAMControllerCorrectfunctionofDRAMInitializationRefreshTimingLimitsScheduletherequesttoDRAMRe OrderRank BankManagementPowerManagementTurnOn OffDRAMSelf Refresh Cont d 55 DRAMControllerBasic GenericDRAMControlle