EDA课程设计 多功能数字钟设计程序清单 数字系统设计与verilog HDL(第四版) 王金明.doc

EDA课程设计多功能数字钟设计程序清单数字系统设计与verilog HDL(第四版) 王金明/*引脚锁定基于DE2一70，芯片为 EP2C70F896，信号定义如下: Clk50m: 50MHz 时钟输，mode:模式选择 0：计时模式 1：设置闹钟模式mcheck:手动调整时间 turn:手动调整时间，在时 、分之间选择change:对选中的数据调整led hourl，led_hour0，led_minul，led_minu0，led_secl,led sec0；alert: 闹钟输出ld_alert: 是否设置了闹钟 ld_hour,id_min,ld_sec：在调整时，指示选中了时，分还是秒*/ module clock(clk50m,mode,turn,change,mreset,led_hour1,led_hour0,led_minu1,led_minu0,led_sec1,led_sec0, alert,ld_alert,ld_check,ld_hour,ld_min,ld_sec);input clk50m;input mode; / key0键input turn; /keyl键input change; / key2 键input mreset; /switch0复位，低电平有效output alert; /gpioO-IOAOoutput ld_alert; /ledgO-led19output ld_check; /ledgl-led22output ld_hour; /ledr3-led13output ld_min; /ledr9-led9output ld_sec; /ledr7-led7output6:0 led_hour1;output6:0 led_hour0;output6:0 led_minu1;output6:0 led_minu0;output6:0led_sec1;output6:0led_sec0;reg 1:0 modestate;/00: 计时模式 10:闹钟模式; 01：手动调整模式；11:非法模式wire nowmode;/记录当前模式，0：计时模式；1: 设置闹钟模式wire ischecking; /是否在手动调整时间assign nowmode, ischecking=modestate;always(negedge mode)/两个按钮都是低电平有效begin case (modestate) 2b00 : modestate=2b10; /设置闹钟模式优先 2b10: modestate=2b01; /手动调整模式 2b01: modestate=2b00; default :modestate=2b00; endcase endwire reset, clk_1hz;switch #(8) rmjitter(clk50m,mresetr,reset);clk50mtol genlhz (clk50m, clk_1hz) ; /生成1Hz的时钟wire 2 : 0 selcode; /对turn信号在不同模式bitsel seldecoder (nowmode, ischecking, turn, selcode, reset);wire 3:0 clocktime0,clocktimel,clocktime2,clocktime3,clocktime4,clockthre5; /计时输出的时钟数值wire clockalarmon; /整点报时的闹钟输出wire 2 : 0 counterselcode; assign counterselcode=(modestate=2b01)?selcode:3b000; counter_time clock_time (clk_1hz,counterselcode,change,clocktime5,clocktime4,clocktime3,clocktime2,clocktime1,clocktime0,clockalarmon,reset); wire3:0 alarmtime0,alarmtime1,alarmtime2,alarmtime3; wire alarmon;alarm_time alarm_time ( clk_1hz , nowmode , selcode 2 : 1 , change , clocktime5, clocktime4, clocktime3, clocktime2, clocktime1,alarmtime3, alarmtime2, alarmtime1, alarmtime0 , alarmon, reset) ;wire voiceout ; alarm alarmvoice (clk50m,clockalarmon, alarmon ,voiceout, raset) ;/显示输出部分assign ld_hour,ld_min,ld_sec=(ischecking|nowmode)?selcode:3b000; assign alert=voiceout;reg3:0 showout2,showout3,showout4,showout5;led led5 (showout5,led_hour1) ; /led译码显示led led4 (showout4,led_hour0) ;led led3 (showout3,led_minu1) ;led led2 (showout2,led_minu0) ;led led1 (clocktime1,led_sec1) ;led led0 (clocktime0,led_sec0) ;always begin if ( nowmode) begin showout5=alarmtime3 ; showout4=alarmtime2 ; showout3=alarmtime1; showout2=alarmtime0 ; end else begin showout5=clocktime5; showout4=clocktime4 ; showout3=clocktime3 ; showout2=clocktime2 ; end end assign ld_alert=nowmode; assign ld_check=ischecking; endmodule/*alarm.V：闹铃模块Clk50m: 50MHz输入时钟 alarmon:闹铃是否打开，2b00:不打开： 2b01：闹钟;2b10:整点报时ala rmoUt:闹铃声音输出 */module alarm(clk50m,alarmon,alarmout,reset);input1:0 alarmon;input clk50m,reset;output reg alarmout;reg15:0 counter_1k;wire clk_1k;assign clk_1k=counter_1k4;always(posedge clk50m)begin if (counter_1k=20) counter_1k=0; else counter_1k=counter_1k+1b1; end wire ddd_du_out,ddd_out; sound_ddd_du ddd_du (clk_1k,alarmon1 ,ddd_du_out) ; sound_ddd ddd(clk_1k,alarmon0,ddd_out); always begin if (!reset) begin if (alarmon 0=1b1) /ddd,闹钟的响铃优先级更高 alarmout=ddd_out ; else if (alarmon=2b10) alarmout=ddd_du_out; else alarmout=0 ; end else alarmout=0 ; endendmodule/*alarm_time.V:闹钟时间设定模块enable:使能信号 Sel：在时、分之间切换选择 10:时；01:分 inc：对选中的信号自增 basetime:基准时钟 */module alarm_time (clk_1hz , enable, sel, inc, basetime, alarmouttime, alarm_on, reset) ;input clk_1hz,enable, inc,reset;input1:0 sel;input4*5-1:0 basetime;output reg alarm_on;output 4*4-1: 0 alarmouttime;reg 3 : 0 hour1, hour0 , minu1, minu0 ; /存储的设定时间always (posedge inc or posedge reset) begin if (reset) /reset=1时复位 begin hour1, hour0,minu1, minu0 =16h0 ; end else begin if (enable) begin if (sel=2b10) /设置时 begin if(hour1,hour0=8h23) hour1,hour0=8h00; else if (hour0=9) begin hour0=0;hour1=hour1+1b1; end else hour0=hour0+1b1; end else if(sel=2b01)/设置分 begin if(minu1,minu0=8h59) minu1,minu0=8h00; else if (minu0=4h9) begin minu0=4h0;minu1=minu1+4h1;end else minu0=minu0+4h1; end else hour1,hour0,minu1,minu0=16h0; end end endalways /闹钟开始条件 beginif(hour1,hour0,minu1,minu0=basetime (4*5-1) :4) & (basetime3:02)alarm_on=1b1; else alarm_on=1b0; endassign alarmouttime= hour1,hour0,minu1,minu0; endmodule/*counter time，v：计时模块，并留有调整接;check:调整信号，3位，分别调整时、分、秒，调整方法:将计数输出给加法器，把调整信息转换成异步置数信息，将加法器的输出作为置数值；hour1，hour0， minul, minu0, sec1，sec0:输出的计时时钟;alarmout:整点报时输出 */module counter_time(clk_1hz,check,inc,hour1,hour0,minu1,minu0,sec1,sec0,alarmout,reset);input clk_1hz,inc,reset;input2:0 check;output3:0 hour1,hour0,minu1,minu0,sec1,sec0;output reg alarmout;reg clk_1hz_md;wire 6: 0 carryclk;reg5:0 incplus;/自增脉冲wire 5 : 0 carry; /进位时钟wire 3 : 0 adderout0,adderout1,adderout2,adderout3,adderout4,adderout5;wire 3 : 0 timerout0,timerout1,timerout2,timerout3,timerout4,timerout5;hexcounter counter_sec0(carryclk0,reset,4d9,4b0,timerout0,carry0);hexcounter counter_sec1(carryclk1,reset,4d5,4b0,timerout1,carry1);hexcounter counter_minu0(carryclk2,reset,4d9,4b0,timerout2,carry2);hexcounter counter_minu1(carryclk3,reset,4d5,4b0,timerout3,carry3);wire 3:0 hour0max;assign hour0max=(timerout5=4h2)?(4h3) : (4h9);hexcounter counter_hour0(carryclk4,reset,hour0max,4b0,timerout4,carry4);hexcounter counter_hour1(carryclk5,reset,4d2,4b0,timerout5,carry5);/每个计时器的时钟，由前级进位和自堦脉冲相加得到assign carryclk0=(check=4h0) ? clk_1hz_md:incplus0; assign carryclk1=carry0|incplus1;assign carryclk2=(check=4h0) ? carry1:incplus2;assign carryclk3=carry2|incplus3;assign carryclk4=(check=4h0) ? carry3:incplus4;assign carryclk5=carry4|incplus5;always /对异步置位信号进行解码begin case (check)3 b001: begin clk_1hz_md=0; incplus=5 b00000, inc ;end3 b010 : begin clk_1hz_md=0; incplus=3b000,inc,2b00;end3 b100 : begin /在正常的调节状态中 clk_1hz_md=0; incplus=1b0, inc, 4b000;enddefault:begin incplus=6b000000; clk_1hz_md=clk_1hz ; endendcase endalwaysbegin if (reset|check)=0)&(timerout3=0) & (timerout2=0) & (timerout12) alarmout=1; /时间小于20秒的时间内else alarmout=0;endassign hour1=timerout5; assign hour0=timerout4;assign minu1=timerout3; assign minu0=timerout2;assign sec1=timerout1; assign sec0=timerout0;endmodule /*Clk50mtol.v: 50mhz 时钟分频到 lhz */module clk50mtol(clk50m,clk1hz);input clk50m;output clk1hz;reg 25:0counter_1hz;/从 50mhz 分频到lhz 的计数器assign clk1hz=counter_1hz14;/assign clk1hz=counter_1hz25;always (posedge clk50m)begin if(counter_1hz=20000) counter_1hz=0; else counter_1hz=counter_1hz+1b1; endendmodule/*led.v:7段数码管(led)译码显示模块 datain:4位，10进制数输入ledout：7位，数码管的7段*/module led(datain,ledout);parameter INWIDTH=4;parameter OUTWIDTH=7;inputINWIDTH-1: 0 datain; output OUTWIDTH-1:0 ledout; regOUTWIDTH-1:0 dataout;assign ledout=dataout;always begincase (datain) 0 : dataout=7b1000000;1 : dataout=7b1111001;2 : dataout=7b0100100;3 : dataout=7b0110000;4 : dataout=7b0011001;5 : dataout=7b0010010;6 : dataout=7b0000010;7 : dataout=7b1111000;8 : dataout=7b0000000;9 : dataout=7b0010000; default : dataout=7b1000000;endcaseendendmodule/*switch-v：对按键开关的消抖电路，采用一个频率较低的时钟，对输入进行采样，消除抖动*/module switch(clk,keyin,keyout);parameter COUNTWIDTH=8;input clk, keyin; output reg keyout; reg COUNTWIDTH-1: 0 counter;wire clk_use; /频率较低的时钟assign clk_use=counter COUNTWIDTH-1;always (posedge clk)counter=counter+1b1;always (posedge clk_use)keyout=keyin;endmodule/*bitsel-v：将输出解码成对时、分、秒的选择(并且分闹钟设置模式还是计时模式)Alarmmode:是否是在设置闹钟模式checkmode：是否是在调整时间模式*/module bitsel(alarmmode, checkmode, sel, selcode, reset) ;input alarmmode, checkmode, sel, reset;output reg 2:0 selcode;reg 2:0 check_code ; reg 1:0 alarm_code ;always (negedge sel or posedge reset)begin if (reset) check_code=3b000; /reset=1 复位 else begin case (check_code) 3 b000: check_code=3 b001; 3 b001: check_code=3 b010; 3 b010: check_code=3 b100; 3 b100: check_code=3 b001; default: check_code=3 b000; endcase end endalways (negedge sel or posedge reset) begin if (reset) alarm_code=2 b00; /低电平复位 else begin case (alarm_code) 2b00 : alarm_code=2b01; 2 b01 : alarm_code=2 b10 ; 2 b10 : alarm_code=2 b01; default : alarm_code=2 b00; endcase end endalways begin if (alarmmodecheckmode) /两个当中只有1个为1 begin if (checkmode) selcode=check_code; else selcode=alarm_code,1b0; end else selcode=3 b000 ; endendmodule/*adder.v:加法器*/module adder(in1, in2, out);parameter in1width=8; parameter in2width=8;parameter outwidth=8;input in1width-1: 0 in1; input in2width-1: 0 in2;outputoutwidth-1: 0 out;assign out=in1+in2;endmodule/*excounter-v：16进制计数的一个计数器*/module hexcounter (clk, set, max, setdata, dataout, carryout) ;input clk,set;input3:0 max,setdata;output carryout;output3:0 dataout;reg3:0 counter;reg carrybit;assign carryout=carrybit; assign dataout=counter;always (posedge clk or posedge set)begin if (set) /set是高电平有效begin counter=setdata; carrybitmax) ) begin counter=0 ; carrybit=1; end else begin counter=counter+1b1; carrybit=0 ; end end endendmodule/*sound_ddd.V:发出嘀嘀嘀闹铃声模块*/module sound_ddd(clk_1k, on, out);parameter soundspace=30;parameter shotstopspace=20; /20ms,两个嘀声的时间距离parameter longstopspace=50; /50ms，连续三个嘀后的时间距离input clk_1k,on;output reg out;reg sound;always (posedge clk_1k)begin sound=sound; endreg10:0 mscount;always (posedge clk_1k)begin if (mscount= (soundspace*3+shotstopspace*2+longstopspace-1) ) mscount=0; else mscount=0) & (mscountsoundspace) ) out=soundspace) & (mscount (soundspace+shotstopspace) ) ) out= (soundspace+shotstopspace) ) & (mscount (soundspace+shotstopspace) +soundspace) ) out= (soundspace+shotstopspace) +soundspace) & (mscount (soundspace+shotstopspace) *2) ) out= (soundspace+shotstopspace) *2)&(mscount (soundspace+shotstopspace) *2+soundspace) ) ) out=sound; else out=0; end else out=0 ; endend