基于VHDL万年历的设计.docx

数字万年历与数字钟的设计一、设计要求数字万年历要求可以任意设定年份月份和日期；当当日时钟走过24时(即0点)后，日期能够自动改变。同样，当每月的最后一天走完后，月份也能够自动显示为下一个月。年份的变化也是如此。时钟计时按照一天24小时计。时钟也可以按照由人工设定当前时间，或者修改当前时间，修改完成后，计时即有当前时间开始。显示方式：日期为2001-11-08，时钟为hh-mm-ss；日期和时钟轮流显示。二、设计原理本设计先用VHDL语言写出需要的各个小模块，并将这些模块进行编译并打包成图形文件，最后将这些图形文件在顶层文件里进行连线，实现具体要求与功能。实验源程序：LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.std_logic_unsigned.ALL;ENTITY onesecond ISPORT (RESET: IN STD_LOGIC; GCLKP1: IN STD_LOGIC; clkout: out std_logic);END onesecond ;ARCHITECTURE Frequency_arch OF onesecond ISSIGNAL Period1S: STD_LOGIC;BEGIN PROCESS( RESET, GCLKP1) VARIABLE Count1 : STD_LOGIC_VECTOR(25 DOWNTO 0); BEGIN IF( GCLKP1EVENT AND GCLKP1=1 ) THEN IF( Count110111110101111000010000000 ) THEN Count1 := 00000000000000000000000000;ELSECount1 := Count1 + 1;END IF;Period1S = Count1(25);- 1MHz END IF; clkout = Period1S; end process;END Frequency_arch;60进制library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt60 isport( clk: in std_logic; ld: in std_logic;da,db:in std_logic_vector(3 downto 0); outa:out std_logic_vector(3 downto 0); outb:out std_logic_vector(3 downto 0); c0: out std_logic);end cnt60;architecture one of cnt60 issignal ma,mb:std_logic_vector(3 downto 0);beginc0=1 WHEN( ma=5 and mb=9 ) else 0 ;process(clk,ld)begin if clkevent and clk=1 thenif ld=1 then ma=da;mb=db; elsif ma=5 and mb=9 thenmb=0000;ma=0000;elsif mb=9 then mb=0000;ma=ma+1;else mb=mb+1; end if; end if;end process;outa=ma;outb=mb;end one;24进制程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt24 isport(clk: in std_logic;ld: in std_logic;da,db:in std_logic_vector(3 downto 0);outa:out std_logic_vector(3 downto 0);outb:out std_logic_vector(3 downto 0);c0: out std_logic);end cnt24;architecture one of cnt24 issignal ma,mb:std_logic_vector(3 downto 0);beginc0=1 WHEN( ma=2 and mb=3 ) else 0 ;process(clk,ld)begin if clkevent and clk=1 thenif ld=1 thenma=da;mb=db; elsif ma=2 and mb=3 thenmb=0000;ma=0000;elsif mb=9 then mb=0000; ma=ma+1;else mb=mb+1; end if; end if;end process;outa=ma;outb=mb;end one;天library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity day isport( clk:in std_logic; ld: in std_logic;maxday: in std_logic_vector(1 downto 0); da:in std_logic_vector(3 downto 0); db:in std_logic_vector(3 downto 0); outa:out std_logic_vector(3 downto 0); outb:out std_logic_vector(3 downto 0); c0: out std_logic);end day;architecture one of day issignal ma: std_logic_vector(3 downto 0);signalmb: std_logic_vector(3 downto 0);beginprocess(clk,ld)beginif clkevent and clk=1 thenif ld=1 then ma=da;mb -28if (ma=2 and mb=8)then ma=0000;mb=0001;c0=1;else if mb=9 then mb=0000;ma=ma+1;c0=0;else mb=mb+1;c0 - 29if (ma=2 and mb=9)then ma=0000;mb=0001;c0=1;else if mb=9 then mb=0000;ma=ma+1;c0=0;else mb=mb+1;c0 - 30if (ma=3 and mb=0)then ma=0000;mb=0001;c0=1;else if mb=9 then mb=0000;ma=ma+1;c0=0;else mb=mb+1;c0 -31if (ma=3 and mb=1)then ma=0000;mb=0001;c0=1;else if mb=9 then mb=0000;ma=ma+1;c0=0;else mb=mb+1;c0=0;end if;end if;end case;end if;end if;end process;outa=ma;outb=mb;end one;月library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yue isport(clk,ld:in std_logic; da: in std_logic_vector(3 downto 0); db: in std_logic_vector(3 downto 0); runnian:in std_logic; outa: out std_logic_vector(3 downto 0); outb: out std_logic_vector(3 downto 0); c0:out std_logic;maxday:out std_logic_vector(1 downto 0) );end yue;architecture one of yue issignal mb:std_logic_vector(3 downto 0);signal ma:std_logic_vector(3 downto 0);beginprocess(clk,ld)begin if (clkevent and clk=1) thenif ld=1 then ma=da;mb=db;if(ma=1 and mb=2)then ma=0000; mb=0001;elsif mb=9 then mb=0000; ma=ma+1; else mb=mb+1;end if;end if;end if; end process;outa=ma;outb=mb;c0=1 WHEN( ma=1 and mb=2 ) else 0 ;maxday =00 when ma=0 and mb=2 and runnian=0else 01 when ma=0 and mb=2 and runnian=1else 10 when (ma=0 and mb=4)or(ma=0 and mb=6)or(ma=0 and mb=9)or(ma=1 and mb=1) else 11;end one;年library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity nian isport( ld1,ld2,clk:in std_logic; dy1,dy2:in std_logic_vector(3 downto 0); y1,y2,y3,y4:out std_logic_vector(3 downto 0); run,cout:out std_logic);end nian;architecture one of nian issignal q1,q2,q3,q4:std_logic_vector(3 downto 0);signal sum,sum1,sum2:std_logic_vector(1 downto 0);begin process(clk,ld1,ld2) begin if clkevent and clk=1 then if ld1=1 then q1=dy1; q2=dy2; elsif ld2=1 then q3=dy1; q4=dy2; else q1=q1+1; if q1=9 then q10); q2=q2+1; end if;if q1=9 and q2=9 then q10);q20);q3=q3+1;end if;if q1=9 and q2=9 and q3=9 then q10);q20);q30); q4=q4+1;end if;if q2=9 and q1=9 and q3=9 and q4=9 then q4=0000;q3=0000;q2=0000;q1=0000;cout=1;else cout=0;end if; end if; end if;end process ;with conv_integer(q4) selectsum1=10 when 1|3|5|7|9, 00 when others;with conv_integer(q2) selectsum2=10 when 1|3|5|7|9, 00 when others; process(q1,q2,q3,q4,sum1,sum2)beginif(q1=0000and q2=0000)thensum=sum1+q3(1 downto 0);else sum=sum2+q1(1 downto 0);end if;end process ; run= 1 whensum=00 else 0;y1=q1;y2=q2;y3=q3;y4=q4;end one;置数选择程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity yima1 is port( x:in std_logic_vector(2 downto 0); y0,y1,y2,y3,y4,y5,y6,y7:out std_logic);end yima1;architecture a of yima1 issignal da:std_logic_vector(7 downto 0);beginwith x select da=00000001when000,00000010when001,00000100when010,00001000when011,00010000when100,00100000when101,01000000when110,10000000when111,00000000when others;y0=da(0);y1=da(1);y2=da(2);y3=da(3);y4=da(4);y5=da(5);y6=da(6);y7 w w null;end case;end if;end process;process (clk,w,ya,yb,yc,yd,ma,mb,da,db,ha,hb,fa,fb,oa,ob)begin if clkevent and clk=1 thencase w iswhen 0 = s0=hb;s1=ha;s2=1111;s3=fa;s4=fb;s5=1111;s6=oa;s7 s0=ya;s1=yb;s2=yc;s3=yd;s4=ma;s5=mb;s6=da;s7=db;end case;end if;end process;with s0 selectd0= 0110000 when 0001,1101101 when 0010,1111001 when 0011,0110011 when 0100,1011011 when 0101,1011111 when 0110,1110000 when 0111,1111111 when 1000,1111011 when 1001,1111110 when others;with s1 selectd1= 0110000 when 0001,1101101 when 0010,1111001 when 0011,0110011 when 0100,1011011 when 0101,1011111 when 0110,1110000 when 0111,1111111 when 1000,1111011 when 1001,1111110 when others;with s2 selectd2= 0110000 when 0001,1101101 when 0010,1111001 when 0011,0110011 when 0100,1011011 when 0101,1011111 when 0110,1110000 when 0111,1111111 when 1000,1111011 when 1001,0000001 when 1111,1111110 when others;with s3 selectd3= 0110000 when 0001,1101101 when 0010,1111001 when 0011,0110011 when 0100,1011011 when 0101,1011111 when 0110,1110000 when 0111,1111111 when 1000,1111011 when 1001,1111110 when others;with s4 selectd4= 0110000 when 0001,1101101 when 0010,1111001 when 0011,0110011