基于vhdl的dds信号发生器的综合电子系统设计报告.docx

综合电子系统设计课程设计报告 （实验一：基于FPGA的DDS信号发生器）姓名：徐久赟学号：041401012班级：0414103班1、 实验要求1) 目的：掌握FPGA设计流程和HDL；掌握DDS原理及其FPGA的实现方法。(2) 实验设备：PC机、Quartus II软件、DE2开发板。(3) 实验内容及说明：要求DDS输出的正弦波频率可变，频率变化范围5Hz-100kHz，频率步进值小于1Hz。2、 设计原理 DDS系统的核心是相位累加器，它由一个累加器和一个N位相位寄存器组成。每来一个时钟脉冲，相位寄存器以步长M增加。相位寄存器的输出与相位控制字相加，其结果作为正弦查找表的地址。正弦查找表由ROM构成，内部存有一个完整周期正弦波的数字幅度信息，每个查找表的地址对应正弦波中0360范围内的一个相位点。查找表把输入的地址信息映射成正弦波的数字幅度信号，加到DAC的输入端，DAC输出的模拟信号经过低通滤波器(LPF)，可得到一个频谱纯净的正弦波。3、 方案论证及详细设计1.系统设计图1：系统框图整个系统由五个模块构成：（1）接口模块，如图2所示。图2：接口模块接口模块提供了方便的操作接口：reset:复位clk:系统时钟（50MHz）clk_en:时钟使能address:地址总线（控制数据总线向对应的寄存器输入数据）见表1address(2位)寄存器00div_reg（时钟分频数）01M_reg10phase_reg11ddsen_reg表1：地址总线表dataBus:数据总线（8位）说明：在接口模块中，内嵌了一个分频器，来控制输出的fclk。通过判断div_reg中的值，分频值从21000000，通过控制fclk进而提高fout，使foutSIN_ROM.mif”。再在文件中加入了头部说明。最后在Quartus中调用了LPM库，生成了sin幅度查询模块。2.系统的顶层逻辑图及DDS的频率精度与频率控制字之间的关系图6：系统顶层逻辑图在DDS原理中，将一个正弦函数用其相位表示，即2pi。同时将其离散化，分成2N个，M为频率控制字，即为每个fclk时钟，将初始相位与其相加，得到下一个相位，进而得到对应幅度值。由fout=M/2N fclk得，M值越大时，此时fout值越大。但是同时，由于M值越大，每次相位累加时，相位值改变的越大，导致幅度值改变的越大。最终生成的正弦函数失真现象越加严重，即频率精度越差。所以，频率精度与频率控制字成反比关系。4、 系统调试及仿真波形图7：FPGA资源利用图8：接口模块仿真图图9：同步模块仿真图图10：相位累加器仿真图图11: 10位加法器5、 系统实现功能输出了一个频率和相位可以调控的正弦波。频率变化范围：1Hz-5MHz,步进值1Hz.6、 设计调试过程中的问题及解决办法由于整个系统由模块化组成，每个模块在设计的过程中都通过波形仿真验证其功能的正确性，使得最终的顶层设计时，没有出现太大的问题。但在整个设计过程中出现了一些软件操作和系统设计的问题。1. 系统编译后无法生成SOF文件。 解决：经查阅资料后了解到，Quartus在没有破解的情况下，不生成SOF文件，最终按照教程破解了软件，成功生成SOF文件。2.DE2开发板上的扩展IO口按键过少，不足以满足整个系统所需。解决：通过增加接口模块，同时增加address控制数据的输入。3. DE2中的DAC芯片为10bit，这样就使得输入的幅度值为10bit，进而使得N只能是10位，导致步进值和输出频率无法同时满足设计需要。 解决：由于DE2的限制，N只能选择10位，所以在接口模块，设计了分频计，这样就可以通过改变fclk减小步进值，使其符合要求。7、 收获、体会及改进设想1. 通过这次的课程设计，重新学习了对Quartus软件的使用，熟练度得到了极大的提高。2. 复习了VHDL语言，对VHDL有了更多的认识，对其使用更加的得心应手。3. 从整体系统的设计到底层各个模块的设计与完善，这种层次化，模块化设计，使得整个系统设计显得更加的科学，极大的降低了系统的出错率。同时对系统各个模块的把握，可以更好的调试与改善整个系统。4. 这样的设计方式，也使得整个系统扩展性得到一定的提高。5. 电子系统的设计应当是层次化，模块化，可调试性强，可扩展性高。优秀的设计思路可以极大的提高整个设计过程的效率。改进设想：1. 频率精度：随着M值的增加会导致波形失真，可以试着给每个M值对应的N值。2. 可扩展性：通过接口模块，可以控制整个系统输出不同的波形。8、 参考文献1 张洪润，张亚凡FPGA/CPLD应用设计200例.上册北京航空航天大学出版社2009.19、 附录1. 接口模块：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity interface is port(reset:in std_logic ;clk:in std_logic;clk_en:in std_logic;address:in std_logic_vector(1 downto 0);dataBus:in std_logic_vector(9 downto 0);fclk:out std_logic;M:out std_logic_vector(9 downto 0);phase:out std_logic_vector(9 downto 0);error:out std_logic;ddsen:out std_logic);end interface;architecture behave of interface is signal div_reg: std_logic_vector(2 downto 0); signal temp :std_logic; signal m_reg: std_logic_vector(9 downto 0); signal phase_reg: std_logic_vector(9 downto 0); signal ddsen_reg: std_logic :=0; signal error_reg: std_logic;begin p1:process(clk)beginif(reset=0)thendiv_reg=000;m_reg=0000000000;phase_regdiv_regm_regphase_regddsen_regerror_reg=1;end case;end if;end process p1;div_frequency:process(clk,clk_en)variable count :integer range 0 to 9999;variable flag :integer;begin if(clk_en=0)thentempflag:=2;when 001=flag:=5;when 010=flag:=10;when 011=flag:=20;when 100=flag:=50;when 101=flag:=100;when 110=flag:=200;when 111=flag:=500;end case;if(count=flag)thencount:=0;temp=not temp;else count:=count+1;end if;end if;end process div_frequency; fclk=temp;M=m_reg;phase=phase_reg;ddsen=ddsen_reg;error=error_reg;end behave;2. 同步模块library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity synchronization is port(flck_in:in std_logic ;m_in:in std_logic_vector(9 downto 0);phase_in:in std_logic_vector(9 downto 0);ddsen:in std_logic;fclk:out std_logic;m:out std_logic_vector(9 downto 0);phase:out std_logic_vector(9 downto 0);end synchronization;architecture behave of synchronization issignal fclk_reg:std_logic;signal m_reg:std_logic_vector(9 downto 0);signal phase_reg:std_logic_vector(9 downto 0);begin process(ddsen)beginif(ddsen=0)thenfclk_reg=0;m_reg=0000000000;phase_reg=0000000000;elsefclk_reg=flck_in;m_reg=m_in;phase_reg=phase_in;end if;end process;fclk=fclk_reg;m=m_reg;phase=phase_reg;end behave;3. 相位累加器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity phase_sum is generic(m_width:integer :=10);port(fclk:in std_logic; m:in std_logic_vector(m_width-1 downto 0); rest:in std_logic; phase_out:out std_logic_vector(m_width-1 downto 0);end phase_sum;architecture behave of phase_sum is signal phase_reg: std_logic_vector(m_width-1 downto 0);signal m_reg: std_logic_vector(m_width-1 downto 0);begin process (fclk)begin if rest=0 then phase_reg=0000000000; elsif (fclkEVENT AND fclk=1) thenphase_reg=phase_reg+m_reg; end if;end process;m_reg=m;phase_out=phase_reg;end behave;4. 10位加法器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity add10 is port(phase_sum_in:in std_logic_vector (9 downto 0);phase_control:in std_logic_vector(9 downto 0);address:out std_logic_vector(9 downto 0);end add10;architecture behave of add10 issignal address_reg:std_logic_vector(10 downto 0);signal phase_sum_reg:std_logic_vector(10 downto 0);signal phase_control_reg:std_logic_vector(10 downto 0);begin phase_sum_reg=0&phase_sum_in;phase_control_reg=0&phase_control;address_reg=phase_sum_reg+phase_control_reg;address=address_reg(9 downto 0);end behave;5. data_rom(调用LPM库生成)- megafunction wizard: %ROM: 1-PORT%- GENERATION: STANDARD- VERSION: WM1.0- MODULE: altsyncram - =- File Name: data_rom.vhd- Megafunction Name(s):- altsyncram- Simulation Library Files(s):- altera_mf- =- *- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!- 7.2 Build 151 09/26/2007 SJ Full Version- *-Copyright (C) 1991-2007 Altera Corporation-Your use of Altera Corporations design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details.LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY data_rom ISPORT(address: IN STD_LOGIC_VECTOR (9 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END data_rom;ARCHITECTURE SYN OF data_rom ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (9 DOWNTO 0);COMPONENT altsyncramGENERIC (clock_enable_input_a: STRING;clock_enable_output_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;ram_block_type: STRING;widthad_a: NATURAL;width_a: NATURAL;width_byteena_a: NATURAL);PORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);END COMPONENT;BEGINq BYPASS,clock_enable_output_a = BYPASS,init_file = SIN_ROM.mif,intended_device_family = Cyclone II,lpm_hint = ENABLE_RUNTIME_MOD=NO,lpm_type = altsyncram,numwords_a = 1024,operation_mode = ROM,outdata_aclr_a = NONE,outdata_reg_a = UNREGISTERED,ram_block_type = M4K,widthad_a = 10,width_a = 10,width_byteena_a = 1)PORT MAP (clock0 = clock,address_a = address,q_a = sub_wire0);END SYN;- =- CNX file retrieval info- =- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC 0- Retrieval info: PRIVATE: AclrAddr NUMERIC 0- Retrieval info: PRIVATE: AclrByte NUMERIC 0- Retrieval info: PRIVATE: AclrOutput NUMERIC 0- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC 0- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC 8- Retrieval info: PRIVATE: BlankMemory NUMERIC 0- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC 0- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC 0- Retrieval info: PRIVATE: Clken NUMERIC 0- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC 0- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING PORT_A- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC 0- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING Cyclone II- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC 0- Retrieval info: PRIVATE: JTAG_ID STRING NONE- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC 0- Retrieval info: PRIVATE: MIFfilename STRING SIN_ROM.mif- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC 1024- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC 2- Retrieval info: PRIVATE: RegAddr NUMERIC 1- Retrieval info: PRIVATE: RegOutput NUMERIC 0- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING 0- Retrieval info: PRIVATE: SingleClock NUMERIC 1- Retrieval info: PRIVATE: UseDQRAM NUMERIC 0- Retrieval info: PRIVATE: WidthAddr NUMERIC 10- Retrieval info: PRIVATE: WidthData NUMERIC 10- Retrieval info: PRIVATE: rden NUMERIC 0- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING BYPASS- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING BYPASS- Retrieval info: CONSTANT: INIT_FILE STRING SIN_ROM.mif- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING Cyclone II- Retrieval info: CONSTANT: LPM_HINT STRING ENABLE_RUNTIME_MOD=NO- Retrieval info: CONSTANT: LPM_TYPE STRING altsyncram- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC 1024- Retrieval info: CONSTANT: OPERATION_MODE STRING ROM- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING NONE- Retrieval info: CONSTANT: OUTDATA_REG_A STRING UNREGISTERED- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING M4K- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC 10- Retrieval info: CONSTANT: WIDTH_A NUMERIC 10- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC 1- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL address9.0- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL q9.0- Retrieval info: CONNECT: address_a 0 0 10 0 address 0 0 10 0- Retrieval info: CONNECT: q 0 0 10 0 q_a 0 0 10 0- Retrieval info: CONNECT: clock0 0 0 0 0 clock 0 0 0 0- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom.vhd TRUE- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom.inc FALSE- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom.cmp FALSE- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom.bsf FALSE- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom_inst.vhd FALSE- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom_waveforms.html FALSE- Retrieval info: GEN_FILE: TYPE_NORMAL data_rom_wave*.jpg FALSE- Retrieval info: LIB_FILE: altera_mf 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