IC_测试报表(包括ESD、老化测试以及所对应的适用标准_E.xls

Test ItemsDetail DescriptionStress conditionSample size lotsRead out hrs eye Spec fail ss Reference standard lotCum IM Infant Mortality Test Early life test Vcc 10 125 C 48hours500DUTs lot30 48hours1 5002 1500 JESD74 JP 001 01 Burn In High Temperature Operation Life HTOL Long term life test Vcc 10 125 C 1000hours 500DUTs lot30 168 500 10001 5002 1500 MIL STD 883E M1005 JESD22 A108C EIAJED 4701 D101 JP 001 01 Ligh Temperature Operation Life LTOL Long term life test Vcc 10 10 C 1000hours THB Temperature Humidity Bias85 C 85 RH 1000 hours77DUTs lot30 168 500 1000hours1 772 231 JESD22 A101 TC Temperature Cycling test 1 65 to 150 C Condition C 500 total cycles or 2 55 to 125 C Condition B 1000 total cycles 77DUTs lot3 1 Test points at 0 100 200 500 cycles 2 Test points at 0 100 500 1000 cycles 1 772 231 JESD22 A104 JEDEC22 A113 MIL STD 883E M1010 PCTPressure Cooker Test 121 2 C 100 RH 2atm Condition Duration A 24 hours 0 2 B 48 hours 0 2 C 96 hours 0 5 D 168 hours 0 5 E 240 hours 0 8 F 336 hours 0 8 77DUTs lot30 1681 772 231 JEDEC STD 22 A102 C EIAJ ED 4701 B 123 PrecondPre Condition Step 1 TCT 65 C 150 C 5 cycles Step 2 Bake 125 C 24 hours Step 3 Soak 30 C 60 RH 192 hours Step 4 IR reflow 260 C 3 Passes Step 5 Scanning Acoustic Microscopy IPC JEDEC J STD 020C JESD22 A113 D ESD Test HBM or MM HBM 2000v MM 100V 3DUTs split 4 splits 3 0 120 36 MIL STD 883E M3015 JEDEC STD 22 A114B JEDEC STD 22 A115A JP 001 Latch up Test Class1 Room Temperature V test 1 5Vcc I test 1 5Icc Class2 Maximum Ambient Temperature V test 1 5Vcc I test 1 5Icc 4DUTs split 2 splits 3 0 80 24 JEDEC78A JP001 01 HCIHot carrier injectionNMOS and PMOS Vg at Max Isub RT2type site 5sites wafer 3wafer lot3 Idsat 10 Idsat0 JESD60 JESD28 TDDBTime dependent dielectric breakdownNMOS and PMOS Vg and Temperature at Max CVS 2types DUT 8DUTs wafer 2wafer lot 2 a The lifetime at 0 01 cumulative failures for a 0 1 cm2 total oxide area or a specified product area b The projected failure rate at 10 years at a target operating voltage temperature and lifetime for a 0 1 cm2 or a specified product total oxide area JP 001 01 VT stabilityThreshold voltage stability BTS 200 C Eg 0 1 0 5 MV cm 60s Cool down Meas VT Heat up 200 C Eg 0 5 0 1MV cm 60s Cool down meas VT 2DUTs wafer 1wafer lot 3 VT VT VT JP 001 01 EMElectromigration 电流密度J 1 5E6A CM2 温度 175 C 20DUTs metal line via Co stack patterns 3 Line via Resistance 20 Ro JP 001 01 TSThermal shock 65 C to 151 C liquid to liquid 77DUTs lot3 Test points at 0 100 200 500 cycles 1 772 231 MIL STD 883E M1011 HASTHighly Accelerated Stress Test 131 C 85 RH 1 1Vcc 96 hours77DUTs lot30 96hoursJESD A110 Notes RHRelative Humidity1 RTRoom Temperature DUTDevice Under Test 2atm2个大气压力 IR reflowInfrared Ray reflow 红外回流 CVSConstant Voltage Stress SATSalt Atmosphere Test MIL STD 883E美国军用标准 BTSBias Temperature Stress TQVTechnology qualification vehicle Test Structure Vehicle Test Parameter 应应用用 标标准准个个人人理理解解 Appropriate technology qualification vehicle TQV Plastic package or other appropriate package Full Functional Burn in with f 100 kHz An appropriate technology qualification vehicle TQV is to be used to get a first view on the expected infant mortality rate of the process Appropriate technology qualification vehicle TQV Plastic package or other appropriate package Full Functional Burn in with f 100 kHz The HTOL test is typically applied on logic and memory devices The LTOL test is intended to look for failures caused by hot carriers and is typically applied on memory devices or devices with submicron device dimensions Appropriate technology qualification vehicle If a dc test structure is designed it should be set up for zero power dissipation under bias and maximum rated voltage for the technology Functional test structures will have transistor leakage Plastic package or other appropriate package Full Functional Test and IDDQ and Leakage Tests 评估IC产品在高温 高湿 偏压条件下对湿气的抵抗能力 加速其失效进程 Appropriate technology qualification vehicle Plastic Package or other appropriate package 评估IC产品中具有不同热膨胀系数的金属之间的界面的接触良率 方法是通过循环流动的空气从高温到低温重复变化 Electric Parameter function ality 评估IC产品在高温 高湿 高气压条件下对湿度的抵抗能力 加速其失效过程 模拟IC在使用之前在一定湿度 温度条件下存储的耐久力 也就是IC从生产到使用之间存储的可靠性 Tests I O and power pins of appropriate technology qualification vehicle Packaged TQV Full Functional Test and IDDQ and Leakage I O and power pins of appropriate technology qualification vehicle Packaged TQV Full Functional Test and IDDQ and Leakage Tests BOTH NMOSFET PMOSFET Minimum and nominal channel length L W if required as allowed by the circuit design rules Wafer Level or Packaged Level Test NMOS and PMOS capacitors preferably transistor arrays reflecting actual circuittopographies The test structure layout should minimize resistive voltage drop Package or Wafer Level tbd NMOS and PMOS transistor structures with or without self heating processed to final metal Wafer or packaged device VT Test structures shall be designed for each combination of line and via contact per JEDEC JESD87 package ceramic or wafer level Rs 评估IC产品中具有不同热膨胀系数的金属之间的界面的接触良率 方法是通过循环流动的液体从高温到低温重复变化 Appropriate technology qualification vehicle If a dc test structure is designed it should be set up