北邮数字逻辑课程设计实验报告(电子钟显示).docx

实验四：电子钟显示一、 实验目的（1）掌握较复杂的逻辑设计和调试。（2）学习用原理图+VHDL语言设计逻辑电路。（3）学习数字电路模块层次设计。（4）掌握ispLEVER 软件的使用方法。（5）掌握ISP 器件的使用。二、实验所用器件和设备在系统可编程逻辑器件ISP1032 一片示波器 一台万用表或逻辑笔 一只TEC-5实验系统，或TDS-2B 数字电路实验系统 一台三、 实验内容数字显示电子钟1、任务要求(1)、时钟的“时”要求用两位显示;上、下午用发光管作为标志；(2)、时钟的“分”、“秒”要求各用两位显示；(3)、整个系统要有校时部分（可以手动，也可以自动），校时时不能产生进位；(4)*、系统要有闹钟部分，声音要响5秒（可以是一声一声的响，也可以连续响）。VHDL源代码：LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; -主体部分-ENTITY clock is port(clk,clr,put,clk1 : in std_logic; - clr 为清零信号，put 为置数脉冲，clk1 为响铃控制时钟choice : in std_logic; -用来选择时钟状态的脉冲信号lighthour : out std_logic_vector(10 downto 0); lightmin : out std_logic_vector(7 downto 0); lightsec : out std_logic_vector(7 downto 0); -输出显示ring : out std_logic); -响铃信号end clock; -60进制计数器模块ARCHITECTURE func of clock is component counter_60 port(clock : in std_logic; clk_1s : in std_logic; putust : in std_logic; clr : in std_logic; load : in std_logic; s1 : out std_logic_vector(3 downto 0); s10 : out std_logic_vector(3 downto 0);co : out std_logic); end component; -24进制计数器模块component counter_24 port(clock : in std_logic; clk_1s : in std_logic; putust : in std_logic; clr : in std_logic; load : in std_logic; s1 : out std_logic_vector(3 downto 0); s10 : out std_logic_vector(6 downto 0); end component; signal sec,a:std_logic; - 2 分频产生1s信号signal l1,l2,l3:std_logic; -判定对时间三部分修改signal c1,c2:std_logic; -进位信号signal load:std_logic_vector(1 downto 0); signal temp:integer range 0 to 2499; signal temp1:integer range 0 to 95; -计数信号signal sec_temp:std_logic_vector(7 downto 0); -总进程begin u1 : counter_60 port map (sec,sec,put,clr,l1,sec_temp(3 downto 0),sec_temp(7 downto 4),c1); u2 : counter_60 port map (c1,sec,put,clr,l2,lightmin(3 downto 0),lightmin(7 downto 4),c2); u3 : counter_24 port map (c2,sec,put,clr,l3,lighthour(3 downto 0),lighthour(10 downto 4); lightsec(7 downto 0) l1=0; -非修改状态l2=0; l3=0; load l1=0; -此状态下对小时进行修改l2=0; l3=1; load l1=0; -此状态下对分钟进行修改 l2=1; l3=0; load l1=1; -此状态下对秒进行修改 l2=0; l3=0; load=00; end case; end if; end process; -计数进程process(clk) beginif (clkevent and clk=1) then -分频if (temp=2499) thentemp = 0; sec=not sec; else temp = temp+1; end if; end if; end process; -响铃进程process(clk1) begin if(clk1event and clk1=1) thenif (temp1=95) thentemp1=0; a=not a; else temp1=temp1+1; end if; end if; end process; ring=a when (c2=1 and sec_temp5 and sec=1) else -5s整点响铃0; end func; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter_60 is port (clock : in std_logic; -计数信号，即低位的进位信号或时钟脉冲信号clk_1s : in std_logic; -周期1s 的时钟信号putust : in std_logic; -调表置数信号clr : in std_logic; -清零load : in std_logic; -判定信号s1 : out std_logic_vector(3 downto 0); -计数器的个位s10 : out std_logic_vector(3 downto 0); -计数器的十位co : out std_logic ); end counter_60; if(load=1 ) -防止脉冲产生进位 co_ temp=0;architecture func of counter_60 is signal s1_temp: std_logic_vector(3 downto 0); signal s10_temp : std_logic_vector(3 downto 0); signal clk,co_temp : std_logic; begin clk=clock when load=0 else putust; process (clk,clr) begin if (clr=1) thens1_temp = 0000; s10_temp = 0000; elsif (clkevent and clk=1)then -进位判断if (s1_temp=9) thens1_temp = 0000;if (s10_temp=5) thens10_temp = 0000; co_temp=1; else co_temp=0;s10_temp = s10_temp+1;end if; elseco_temp=0; s1_temp = s1_temp+1; end if; end if; end process; s1 = s1_temp when (clk_1s=1or load=0) else1111; s10 = s10_temp when (clk_1s=1 or load=0) else1111; co = co_temp when (load=0) else0; end func; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -24进制计数器entity counter_24 is port(clock : in std_logic; -计数信号clk_1s : in std_logic; -周期1s 的时钟信号putust : in std_logic; clr : in std_logic; -清零信号load : in std_logic; -判定信号s1 : out std_logic_vector(3 downto 0); -计数器的个位s10 : out std_logic_vector(6 downto 0); -计数器的十位end counter_24; architecture func of counter_24 is signal s1_temp : std_logic_vector(3 downto 0); signal s10_temp : std_logic_vector(1 downto 0); signal clk : std_logic; begin clk=clock when load=0 else putust; process (clk,clr) begin if (clr=1) thens1_temp = 0000; s10_temp = 00; elsif (clkevent and clk=1) then if (s1_temp=3 and s10_temp=2) thens1_temp = 0000;s10_temp = 00; elsif (s1_temp=9) thens1_temp=0000; s10_temp=s10_temp+1;else s1_temp s10 s10 s10 null; end case; else s10=0000000; end if; end process; s1 = s1_temp when (clk_1s=1 or load=0) else 1111; end func;四、 实验小结：注意当时钟处于被修改