串行10位数模转换器TLC5615英文手册.doc

12348765DINSCLKCSDOUTVDDOUTREFINAGNDTLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST200310-BITDIGITAL-TO-ANALOGCONVERTERSFEATURESSettlingTimeto0.5LSB.12.5sTypMonotonicOverTemperature10-BitCMOSVoltageOutputDACinan8-TerminalPackagePinCompatibleWiththeMaximMAX5155-VSingleSupplyOperationAPPLICATIONS3-WireSerialInterfaceBattery-PoweredTestInstrumentsHigh-ImpedanceReferenceInputsDigitalOffsetandGainAdjustmentVoltageOutputRange.2TimestheRefer-enceInputVoltageBatteryOperated/RemoteIndustrialControlsInternalPower-OnResetMachineandMotionControlDevicesLowPowerConsumption.1.75mWMaxCellularTelephonesUpdateRateof1.21MHzD,P,ORDGKPACKAGE(TOPVIEW)DESCRIPTIONTheTLC5615isa10-bitvoltageoutputdigital-to-analogconverter(DAC)withabufferedreferenceinput(highimpedance).TheDAChasanoutputvoltagerangethatistwotimesthereferencevoltage,andtheDACismonotonic.Thedeviceissimpletouse,runningfromasinglesupplyof5V.Apower-on-resetfunctionisincorporatedtoensurerepeatablestart-upconditions.DigitalcontroloftheTLC5615isoverathree-wireserialbusthatisCMOScompatibleandeasilyinterfacedtoindustrystandardmicroprocessorandmicrocontrollerdevices.Thedevicereceivesa16-bitdatawordtoproducetheanalogoutput.ThedigitalinputsfeatureSchmitttriggersforhighnoiseimmunity.DigitalcommunicationprotocolsincludetheSPI,QSPI,andMicrowirestandards.The8-terminalsmall-outlineDpackageallowsdigitalcontrolofanalogfunctionsinspace-criticalapplications.TheTLC5615Cischaracterizedforoperationfrom0Cto70C.TheTLC5615Iischaracterizedforoperationfrom-40Cto85C.AVAILABLEOPTIONSPACKAGESMALLOUTLINEPLASTICSMALLOUTLINEPLASTICDIPTA(1)(D)(DGK)(P)0Cto70CTLC5615CDTLC5615CDGKTLC5615CP40Cto85CTLC5615IDTLC5615IDGKTLC5615IP(1)AvailableintapeandreelastheTLC5615CDRandtheTLC5615IDRSPI,QSPIaretrademarksofMotorola,Inc.MicrowireisatrademarkofNationalSemiconductorCorporation.Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.PRODUCTIONDATAinformationiscurrentasofpublicationdate.Copyright19962003,TexasInstrumentsIncorporatedProductsconformtospecificationsperthetermsofTexasInstrumentsstandardwarranty.P_+DAC10-Bit DAC RegisterPower-ONResetControlLogic16-Bit Shift Register4DummyBits20s10 Data Bits(LSB)(MSB)REFINAGNDCSSCLKDINOUT(Voltage Output)_+DOUTRR 2TLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST2003FUNCTIONALBLOCKDIAGRAMTerminalFunctionsTERMINALI/ODESCRIPTIONNAMENO.DIN1ISerialdatainputSCLK2ISerialclockinputCS3IChipselect,activelowDOUT4OSerialdataoutputfordaisychainingAGND5AnaloggroundREFIN6IReferenceinputOUT7ODACanalogvoltageoutputVDD8PositivepowersupplyABSOLUTEMAXIMUMRATINGSoveroperatingfree-airtemperaturerange(unlessotherwisenoted)(1)UNITSupplyvoltage(VDDtoAGND)7VDigitalinputvoltagerangetoAGND-0.3VtoVDD+0.3VReferenceinputvoltagerangetoAGND-0.3VtoVDD+0.3VOutputvoltageatOUTfromexternalsourceVDD+0.3VContinuouscurrentatanyterminal20mAOperatingfree-airtemperaturerange,TATLC5615C0Cto70CTLC5615I-40Cto85CStoragetemperaturerange,Tstg-65Cto150CLeadtemperature1,6mm(1/16inch)fromcasefor10seconds260C(1)Stressesbeyondthoselistedunder,absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder,recommendedoperatingconditions”isnotimplied.ETLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST2003RECOMMENDEDOPERATINGCONDITIONSMINNOMMAXUNITSupplyvoltage,VDD4.555.5VHigh-leveldigitalinputvoltage,VIH2.4VLow-leveldigitalinputvoltage,VIL0.8VReferencevoltage,VreftoREFINterminal22.048VDD-2VLoadresistance,RL2kTLC5615C070COperatingfree-airtemperature,TATLC5615I4085CELECTRICALCHARACTERISTICSoverrecommendedoperatingfree-airtemperaturerange,VDD=5V5%,Vref=2.048V(unlessotherwisenoted)STATICDACSPECIFICATIONSPARAMETERTESTCONDITIONSMINTYPMAXUNITResolution10bitsIntegralnonlinearity,endpointadjusted(INL)Vref=2.048V,See(1)1LSBDifferentialnonlinearity(DNL)Vref=2.048V,See(2)0.10.5LSBEZSZero-scaleerror(offseterroratzeroscale)Vref=2.048V,See(3)3LSBZero-scale-errortemperaturecoefficientVref=2.048V,See(4)3ppm/CEGGainerrorVref=2.048V,See(5)3LSBGain-errortemperaturecoefficientVref=2.048V,See(6)1ppm/CZeroscale80PSRRPower-supplyrejectionratioSee(7)(8)dBGain80AnalogfullscaleoutputRL=100k2Vref(1023/1024)V(1)Therelativeaccuracyorintegralnonlinearity(INL),sometimesreferredtoaslinearityerror,isthemaximumdeviationoftheoutputfromthelinebetweenzeroandfullscaleexcludingtheeffectsofzerocodeandfull-scaleerrors(seetext).Testedfromcode3tocode1024.(2)Thedifferentialnonlinearity(DNL),sometimesreferredtoasdifferentialerror,isthedifferencebetweenthemeasuredandideal1LSBamplitudechangeofanytwoadjacentcodes.Monotonicmeanstheoutputvoltagechangesinthesamedirection(orremainsconstant)asachangeinthedigitalinputcode.Testedfromcode3tocode1024.(3)Zero-scaleerroristhedeviationfromzero-voltageoutputwhenthedigitalinputcodeiszero(seetext).(4)Zero-scale-errortemperaturecoefficientisgivenby:EZSTC=EZS(Tmax)-EZS(Tmin)/Vref106/(Tmax-Tmin).(5)Gainerroristhedeviationfromtheidealoutput(Vref-1LSB)withanoutputloadof10kexcludingtheeffectsofthezero-scaleerror.(6)Gaintemperaturecoefficientisgivenby:EGTC=EG(Tmax)-EG(Tmin)/Vref106/(Tmax-Tmin).(7)Zero-scale-errorrejectionratio(EZS-RR)ismeasuredbyvaryingtheVDDfrom4.5Vto5.5Vdcandmeasuringtheproportionofthissignalimposedonthezero-codeoutputvoltage.(8)Gain-errorrejectionratio(EG-RR)ismeasuredbyvaryingtheVDDfrom4.5Vto5.5Vdcandmeasuringtheproportionofthissignalimposedonthefull-scaleoutputvoltageaftersubtractingthezero-scalechange.VOLTAGEOUTPUT(OUT)PARAMETERTESTCONDITIONSMINTYPMAXUNITVOVoltageoutputrangeRL=10k0VDD-0.4VOutputloadregulationaccuracyVO(OUT)=2V,RL=2k0.5LSBIOSCOutputshortcircuitcurrentOUTtoVDDorAGND20mAVOL(low)Outputvoltage,low-levelIO(OUT)5mA0.25VVOH(high)Outputvoltage,high-levelIO(OUT)-5mA4.75VREFERENCEINPUT(REFIN)VIInputvoltage0VDD-2VriInputresistance10M3TLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST2003VOLTAGEOUTPUT(OUT)(continued)PARAMETERTESTCONDITIONSMINTYPMAXUNITCiInputcapacitance5pFDIGITALINPUTS(DIN,SCLK,CS)VIHHigh-leveldigitalinputvoltage2.4VVILLow-leveldigitalinputvoltage0.8VIIHHigh-leveldigitalinputcurrentVI=VDD1AIILLow-leveldigitalinputcurrentVI=01ACiInputcapacitance8pFDIGITALOUTPUT(DOUT)VOHOutputvoltage,high-levelIO=-2mAVDD-1VVOLOutputvoltage,low-levelIO=2mA0.4VPOWERSUPPLYVDDSupplyvoltage4.555.5VVDD=5.5V,Noload,Vref=0150250AAllinputs=0VorVDDIDDPowersupplycurrentVDD=5.5V,Noload,Vref=2.048V230350AAllinputs=0VorVDDANALOGOUTPUTDYNAMICPERFORMANCEVref=1Vppat1kHz+2.048Vdc,Signal-to-noise+distortion,S/(N+D)code=1111111111,60dBSee(1)(1)Thelimitingfrequencyvalueat1Vppisdeterminedbytheoutput-amplifierslewrate.DIGITALINPUTTIMINGREQUIRMENTS(SEEFIGURE1)PARAMETERMINNOMMAXUNITtsu(DS)Setuptime,DINbeforeSCLKhigh45nsth(DH)Holdtime,DINvalidafterSCLKhigh0nstsu(CSS)Setuptime,CSlowtoSCLKhigh1nstsu(CS1)Setuptime,CShightoSCLKhigh50nsth(CSH0)Holdtime,SCLKlowtoCSlow1nsth(CSH1)Holdtime,SCLKlowtoCShigh0nstw(CS)Pulseduration,minimumchipselectpulsewidthhigh20nstw(CL)Pulseduration,SCLKlow25nstw(CH)Pulseduration,SCLKhigh25nsOUTPUTSWITCHINGCHARACTERISTICSPARAMETERTESTCONDITIONSMINNOMMAXUNITtpd(DOUT)Propagationdelaytime,DOUTCL=50pF50nsOPERATINGCHARACTERISTICSoverrecommendedoperatingfree-airtemperaturerange,VDD=5V5%,Vref=2.048V(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITANALOGOUTPUTDYNAMICPERFORMANCECL=100pF,SROutputslewrateRL=10k,0.30.5V/sTA=25C4th(CSH0)tsu(CSS)tw(CH)tw(CL)th(CSH1)tsu(CS1)tw(CS)tpd(DOUT)CSSCLKDINDOUTtsu(DS)th(DH)NOTES:A.The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.See Note ASee Note ASee Note BMSBLSBB.Data input from preceeding conversion cycle.See Note CPrevious LSBC.Sixteenth SCLK falling edgeTLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST2003OPERATINGCHARACTERISTICS(continued)overrecommendedoperatingfree-airtemperaturerange,VDD=5V5%,Vref=2.048V(unlessotherwisenoted)PARAMETERTESTCONDITIONSMINTYPMAXUNITANALOGOUTPUTDYNAMICPERFORMANCETo0.5LSB,CL=100pF,tsOutputsettlingtime12.5sRL=10k,See(1)GlitchenergyDIN=All0stoall1s5nVsREFERENCEINPUT(REFIN)ReferencefeedthroughREFIN=1Vppat1kHz+2.048Vdc(see(2)-80dBReferenceinputREFIN=0.2Vpp+2.048Vdc30kHzbandwidth(f-3dB)(1)Settlingtimeisthetimefortheoutputsignaltoremainwithin0.5LSBofthefinalmeasuredvalueforadigitalinputcodechangeof000hexto3FFhexor3FFhexto000hex.(2)ReferencefeedthroughismeasuredattheDACoutputwithaninputcode=000hexandaVrefinput=2.048Vdc+1Vppat1kHz.PARAMETERMEASURMENTINFORMATIONFigure1.TimingD1510502025303.43.23VDD = 5 VVREFIN = 2.048 VTA = 25C- Output Source Current - mAIO VO - Output Pullup Voltage - V860.6- Output Sink Current - mA1014160.8141218VDD = 5 VVREFIN = 2.048 VTA = 25CIO VO - Output Pulldown Voltage - V80- Supply Current -200280240160120400-60-40-20020406080100120140At - Temperature - CVDD = 5 VVREFIN = 2.048 VTA = 25CIDD11001 k10 k100 kG - Relative Gain - dB420-2-4-6-8-10-12-14VDD = 5 VVREFIN = 0.2 VPP + 2.048 V dcTA = 25CfI - Input Frequency - HzTLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST2003TYPICALCHARACTERISTICSOUTPUTSINKCURRENTOUTPUTSOURCECURRENTvsvsOUTPUTPULLDOWNVOLTAGEOUTPUTPULLUPVOLTAGEFigure2.Figure3.VREFINTOV(OUT)SUPPLYCURRENTRELATIVEGAINvsvsTEMPERATUREINPUTFREQUENCYFigure4.F40501 kSignal-To-Noise + Distortion - dB7030Frequency - Hz201006010 k100 k300 kVDD = 5 VTA = 25CVREFIN = 4 VPPDifferential Nonlinearity LSB00.050.150.050.10.15Input Code25551176710230Integral Nonlinearity LSB0.6Input Code100.2255511767102301TLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST2003TYPICALCHARACTERISTICS(continued)SIGNAL-TO-NOISE+DISTORTIONvsINPUTFREQUENCYATREFINFigure6.Figure7DifferentialNonlinearityWithInputCodeFigure8IntegralNonlinearityWithInputC_+ResistorStringDAC5 V0.1 FAGNDVDDOUTREFINDINSCLKCSDOUTRR_+2搠VREFIN搠102310242搠VREFIN搠51310242搠VREFIN搠5121024+VREFIN2搠VREFIN搠51110242搠VREFIN搠11024TLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST2003APPLICATIONINFORMATIONGENERALFUNCTIONTheTLC5615usesaresistorstringnetworkbufferedwithanopampinafixedgainof2toconvert10-bitdigitaldatatoanalogvoltagelevels(seefunctionalblockdiagramandFigure9).TheoutputoftheTLC5615isthesamepolarityasthereferenceinput(seeTable1).AninternalcircuitresetstheDACregistertoallzerosonpowerup.Figure9.TLC5615TypicalOperatingCircuitTable1.BinaryCodeTable(0Vto2VREFINOutput),Gain=2INPUT(1)OUTPUT1111111111(00):1000000001(00)1000000000(00)0111111111(00):0000000001(00)0000000000(00)0V(1)A10-bitdatawordwithtwobitsbelowtheLSBbit(sub-LSB)with0valuesmustbewrittensincetheDACinputlatchis12bitswide.BUFFERAMPLIFIERTheoutputbufferhasarail-to-railoutputwithshortcircuitprotectionandcandrivea2-kloadwitha100-pFloadcapacitance.Settlingtimeis12.5stypicaltowithin0.5LSBf(SCLK)max+1twCH)twCLtp(CS)+16 twCH)twCL)twCS10 Data Bitsxx12 BitsMSBLSB2 Extra (Sub-LSB) Bitsx = dont care10 Data Bitsxx16 BitsMSBLSB2 Extra (Sub-LSB) Bits4 Upper Dummy Bitsx = dont careTLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST2003EXTERNALREFERENCEThereferencevoltageinputisbuffered,whichmakestheDACinputresistancenotcodedependent.Therefore,theREFINinputresistanceis10MandtheREFINinputcapacitanceistypically5pFindependentofinputcode.ThereferencevoltagedeterminestheDACfull-scaleoutput.LOGICINTERFACEThelogicinputsfunctionwitheitherTTLorCMOSlogiclevels.However,usingrail-to-railCMOSlogicachievesthelowestpowerdissipation.Thepowerrequirementincreasesbyapproximately2timeswhenusingTTLlogiclevels.SERIALCLOCKANDUPDATERATEFigure1showstheTLC5615timing.Themaximumserialclockrateis:orapproximately14MHz.Thedigitalupdaterateislimitedbythechip-selectperiod,whichis:andisequalto820nswhichisa1.21MHzupdaterate.However,theDACsettlingtimeto10bitsof12.5slimitstheupdaterateto80kHzforfull-scaleinputsteptransitions.SERIALINTERFACEWhenchipselect(CS)islow,theinputdataisreadintoa16-bitshiftregisterwiththeinputdataclockedinmostsignificantbitfirst.TherisingedgeoftheSLCKinputshiftsthedataintotheinputregister.TherisingedgeofCSthentransfersthedatatotheDACregister.WhenCSishigh,inputdatacannotbeclockedintotheinputregister.AllCStransitionsshouldoccurwhentheSCLKinputislow.Ifthedaisychain(cascading)function(seedaisy-chainingdevicessection)isnotused,a12-bitinputdatasequencewiththeMSBfirstcanbeusedasshowninFigure10:Figure10.12-BitInputDataSequenceor16bitsofdatacanbetransferredasshowninFigure11withthe4upperdummybitsfirst.Figure11.16-BitInputDataSSCLKDINCSDOUTTLC5615SKSOI/OSIMicrowirePortNOTE A:The DOUT-SI connection is not required for writing tothe TLC5615 but may be used for verifying datatransfer if desired.SCLKDINCSDOUTTLC5615SCKMOSII/OMISOSPI/QSPIPortNOTE A:The DOUT-MISO connection is not required for writing to theTLC5615 but may be used for verifying data transfer.CPOL = 0, CPHA = 0TLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST2003ThedatafromDOUTrequires16fallingedgesoftheinputclockand,therefore,requiresanextraclockwidth.WhendaisychainingmultipleTLC5615devices,thedatarequires4upperdummybitsbecausethedatatransferrequires16input-clockcyclesplusoneadditionalinput-clockfallingedgetoclockoutthedataattheDOUTterminal(seeFigure1).Thetwoextra(sub-LSB)bitsarealwaysrequiredtoprovidehardwareandsoftwarecompatibilitywith12-bitdataconvertertransfers.TheTLC5615three-wireinterfaceiscompatiblewiththeSPI,QSPI,andMicrowireserialstandards.ThehardwareconnectionsareshowninFigure12andFigure13.TheSPIandMicrowireinterfacestransferdatain8-bitbytes,therefore,twowritecyclesarerequiredtoinputdatatotheDAC.TheQSPIinterface,whichhasavariableinputdatalengthfrom8to16bits,canloadtheDACinputregisterinonewritecycle.Figure12.MicrowireConnectionFigure13.SPI/QSPIConnectionDAISY-CHAININGDEVICESDACscanbedaisy-chainedbyconnectingtheDOUTterminalofonedevicetotheDINofthenextdeviceinthechain,providingthatthesetuptime,tsu(CSS),(CSlowtoSCLKhigh)isgreaterthanthesumofthesetuptime,tsu(DS),plusthepropagationdelaytime,tpd(DOUT),forpropertiming(seedigitalinputtimingrequirementssection).ThedataatDINappearsatDOUT,delayedby16clockcyclesplusoneclockwidth.DOUTisatotem-poledoutputforlowpower.DOUTchangesontheSCLKfallingedgewhenCSislow.WhenCSishigh,DOUTDAC CodeOutputVoltage0 VNegativeOffsetTLC5615C,TLC5615ISLAS142DOCTOBER1996REVISEDAUGUST2003LINEARITY,OFSET,ANDGAINERRORUSINGSINGLEENDEDSUPPLIESWhenanamplifierisoperatedfromasinglesupply,thevoltageoffsetcanstillbeeitherpositiveornegative.Withapositiveoffset,theoutputvoltagechangesonthefirstcodechange.Withanegativeoffsettheoutputvoltagemaynotchangewiththefirstcodedependingonthemagnitudeoftheoffsetvoltage.Theoutputamplifierattemptstodrivetheoutputtoanegativevoltage.However,becausethemostnegativesupplyrailisground,theoutputcannotdrivebelowgroundandclampstheoutputat0V.Theoutputvoltagethenremainsatzerountiltheinputcodevalueproducesasufficientpositiveoutputvoltagetoovercomethenegativeoffsetvoltage,resultinginthetransferfunctionshowninFigure14.Figure14.EffectofNegativeOffset(SingleSupply)Thisoffseterror,notthelinearityerror,producesthisbreakpoint.Thetransferfunctionwouldhavefollowedthedottedlineiftheoutputbuffercoulddrivebelowthegroundrail.ForaDAC,linearityismeasuredbetweenzero-inputcode(allinputs0)andfull-scalecode(allinputs1)afteroffsetandfullscaleareadjustedoutoraccountedforinsomeway.However,singlesupplyoperationdoesnotallowforadjustmentwhentheoffsetisnegativeduetothebreakpointinthetransferfunction.Sothelinearityismeasuredbetweenfull-scalecodeandthelowestcodethatproducesapositiveoutputvoltage.FortheTLC5615,thezero-scale(offset)errorisplusorminus3LSBmaximum.Thecodeiscalculatedfromthemaximumspecificationforthenegativeoffset.POWER-SUPPLYBYPASSINGANDGROUNDMANAGEMENTPrinted-circuitboardsthatuseseparateanaloganddigitalgroundplanesofferthebestsystemperformance.Wire-wrapboardsdonotperformwellandshouldnotbeused.Thetwogroundplanesshouldbeconnectedtogetheratthelow-impedancepower-supplysource.ThebestgroundconnectionmaybeachievedbyconnectingtheDACAGNDterminaltothesystemanaloggroundplanemakingsurethatanaloggroundcurrentsarewellmanagedandtherearenegligiblevoltagedropsacrossthegroundplane.A0.1-Fceramic-capacitorbypassshouldbeconnectedbetweenVDDandAGNDandmountedwithshortleadsascloseaspossibletothedevice.Useofferritebeadsmayfurtherisolatethesystemanalogsu