一般计数器的VHDL设计.doc

实验三 一般计数器的VHDL设计实验报告 (1) 实验目的：学习一般计数器的设计、仿真和硬件测试，进一步熟悉VHDL设计技术。(2) 实验内容1：用VHDL设计含异步清0和同步时钟使能的十进制加法计数器。提示：参考例3-21。要求：在Quartus上进行编辑、编译、综合、适配、仿真，给出其所有信号的时序仿真波形。引脚锁定以及硬件下载测试。选择目标器件EP1C3，建议选实验电路模式5，模式图如附录1附图6所示。(3) 实验内容2：用VHDL设计含异步清0和同步时钟使能的十进制加减可控计数器。提示：在例3-21的基础上进行修改。要求：在Quartus上进行编辑、编译、综合、适配、仿真，给出其所有信号的时序仿真波形。(4) 程序设计程序1：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport(clk,rst,en:in std_logic;cq:out std_logic_vector(3 downto 0);cout:out std_logic);end entity cnt10;architecture behav of cnt10 isbeginprocess(clk,rst,en)variable cqi:std_logic_vector(3 downto 0);beginif rst=1 then cqi:=(others=0);elsif clkevent and clk=1 thenif en=1 thenif cqi0);end if;end if;end if;if cqi=9 then cout = 1;else cout=0;end if;cq 0); ELSIF CLKEVENT AND CLK=1 THEN IF EN=1 THEN IF MDE = 1 THEN IF CQI 0); END IF;ELSIF CQI 0 THEN CQI := CQI - 1;ELSE CQI := “1001”; END IF; END IF;END IF;IF MDE=1 THENIF CQI = 9 THEN COUT = 1;ELSE COUT = 0;END IF;ELSIF CQI = 0 THEN COUT = 1;ELSE COUT = 0;END IF;CQ LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S NULL ; END CASE ; END PROCESS P1;END;程序2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY WJ ISPORT(clock0,ret0,ena0:IN STD_LOGIC;led : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);cout0: OUT STD_LOGIC);END ENTITY WJ;ARCHITECTURE TWO OF WJ ISCOMPONENT CNT4BPORT(CLK,RST,EN: IN STD_LOGIC;OUTY: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT: OUT STD_LOGIC);END COMPONENT;COMPONENT DECL7SPORT(A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);LED7S: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END COMPONENT;SIGNAL tmp: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINu1: CNT4B PORT MAP(CLK=clock0,EN=ena0,RST=ret0,OUTY=tmp,COUT=cout0);u2: DECL7S PORT MAP(A=tmp,LED7S=led);END ARCHITECTURE TWO;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4B ISPORT(CLK,RST,EN : IN STD_LOGIC;OUTY: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT: OUT STD_LOGIC);END ENTITY CNT4B;ARCHITECTURE BHV OF CNT4B ISBEGINPROCESS(CLK,EN,RST)VARIABLE CQI: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF RST=1 THEN CQI:=(OTHERS=0);ELSIF CLKEVENT AND CLK=1 THENIF EN=1 THENIF CQI0); END IF;END IF;END IF;IF CQI=1111 THEN COUT=1;ELSE COUT=0; END IF;OUTY LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S NULL;END CASE;END PROCESS;END ARCHITECTURE ONE;（6）实验过程过程同实验三一样。(7)仿真波形图1 程序