外文翻译--单片集成MEMS技术

Monolithically integrated MEMS technologyIn the past 20 years, CMOS technology has become a major integrated circuit manufacturing technology, manufacturing costs decline at the same time, yield and production has also been greatly improved, COMS technology will continue to increase integration and reduce development of a special size. Today, CMOS integrated process not only be used in the design of integrated circuits, but also to be used in many micro-sensors and micro-actuator, so it can be integrated circuits and micro-sensor integrated with a powerful, intelligent sensors. With micro-sensor constantly expanding the scope of application of the sensor increasingly high demands of the future microsensor the main requirements are: miniaturization and integration of low-power and low-cost high-precision and long life； - and intelligent. Micromachined silicon integrated circuits and the integration of integration, to meet the above-mentioned requirements. At present, the majority of products integrated sensor using hybrid integrated, monolithic integration of a very small percentage. And the realization of single-chip integration is the key to achieving intelligent sensors, in particular monolithic integrated MEMS sensor technology is todays system-on-chip can achieve one of the key technologies. Clearly, monolithic integration of the various technical difficulties analysis of MEMS and have already given the various monolithic integration of MEMS technology is essential.1. Monolithic integration of MEMS technology advantages and the challenges facing。MEMS and CMOS achieve working together, the separate manufacturing CMOS MEMS sensors and integrated circuits, and then cut from their chips, fixed in a common substrate, and, bonded connection, thereby bringing the two integration, This is the so-called mixed (hybrid) method. This method does not produce MEMS manufacturing process for CMOS circuits pollution At the same time, both the production process Noninterference. However, due to signal bonding point and fuses, resulting in high-frequency applications, decline in the quality of signal transmission, and to develop two production lines to increase the cost of the product. In order to address some performance issues, and lower manufacturing costs, and proposed to do in the part of MEMS and CMOS circuits with a substrate, which is produced compatible with CMOS technology or monolithic integrated MEMS technology called CMOS-MEMS technology. This method relative hybrid method generally have the following advantages: First, the performance can be greatly improved, because parasitic capacitance and crosstalk phenomenon can be significantly reduced； second, hybrid method requires sophisticated technology to reduce packaging Sensor Interface affected, and monolithic integration requires packaging technology is relatively simple and therefore, lower cost sensors； third, monolithic integrated sensor array sensor technology is the need to overcome the array sensor and external decoding circuit an effective interconnect bottleneck； Fourth, the development of monolithic integrated mixed development of MEMS products than MEMS products for a short time, and to develop low cost.Monolithic integration of MEMS technology under some of MEMS devices and CMOS circuit can be divided into different order processing before CMOS (pre-CMOS), mixed CMOS (intermediate-CMOS), and after the CMOS (post-CMOS) integrated approach.Post-CMOS approach is in the processing of silicon CMOS circuits End, through some additional MEMS micro-processing technology to achieve monolithic integrated MEMS system, at present, monolithic integration of MEMS technology in this way mainly based. Post-CMOS approach is the main issue on MEMS processing temperature CMOS circuit performance in front of an impact on more serious is that the technology behind high-temperature MEMS processing temperature and metal CMOS process ahead of incompatibility. In the present study as the most polysilicon layer structure of the MEMS example, the densification of phosphorus glass annealing temperature is 950 due to a structural polysilicon layer of stress annealing temperature reached 1050 , which will enable CMOS devices junction depth migration occurred. In particular 800 shallow junction devices junction depth migration will affect device performance. On the other hand, the conventional aluminum metallization process, when the temperature reaches 400-450 , the reliability of CMOS circuits will be severely affected. From the above we can see that: how to overcome behind high-temperature MEMS processing temperature on the micro-structure of the front end processing has been the impact of CMOS circuits integrated MEMS single-chip solution is key to the system. At present, the international community is essential to resolve this issue through three ways: First is the interconnection of refractory metals instead of aluminum metal interconnect, for example, the University of Berkeley to replace tungsten aluminum metal interconnect programmes, such follow-up increased tolerance MEMS processing for high temperature； The second is produced by finding low temperature mechanical properties and excellent substitute materials as structural polysilicon layer； third way is to use its existing structure CMOS MEMS layer as a layer structure.Pre-CMOS integrated approach is to create structure MEMS manufacturing CMOS circuits, although this integrated CMOS technology to overcome post-CMOS method of high-temperature MEMS Technology on CMOS circuits affected, but because of the existence of micro-vertical structure, and therefore, there sensor and circuit interconnection level coverage, but also in the process of CMOS circuits on the micro-structure protection is also a need to consider the issue. Even fine-tune the optimization of CMOS process, such as: gate oxide may be heavily doped layer impact of the structure. In addition, the MEMS technology can not process any of the metal or other materials, such as piezoelectric polymers, and so on, makes this method only suitable for some special applications.Intermediate-CMOS circuits in the CMOS production process to insert some MEMS micro-processing technology to achieve monolithic integrated MEMS approach. This approach has been very mature and have a lot of commercialization of products, is the first study of a single-chip integration method is to solve the pre - and post-CMOS CMOS method effective method problems, but due to the need for the existing standard CMOS or larger BiCMOS process changes, therefore, the use of this method is limited.2.The main monolithic integrated MEMS technology statusAt present, the monolithic integration of MEMS technology mainly to post-CMOS technologies, through a series of compatible with CMOS process on the surface micro-machining and processing to achieve monolithic integration of MEMS. Can be divided into two kinds: one is in the top layer CMOS structure to a structure layer deposition micro-machining； the other is directly CMOS layer structure as the original structure of the MEMS micro-machined.2.1 Deposition of new structural materials for the structure of integrated MEMS technology2.1.1 Polysilicon layer structure as the surface micro-machining technology integrationThis process is typical of modules developed at the University of Berkeley Integrated CMOS and MEMS Technology (modular integration of CMOS with micro-structures, MICS), this method is for the micro-structural polysilicon layer, phosphorus silicon glass (PSG) as a sacrificial layer The surface micro-machining technology. A refractory metal tungsten metal interconnect instead of aluminum metal interconnect to bear behind the polysilicon production needs of micro-structure of high-temperature, but at 600 , tungsten and silicon form easily response by the University of Berkeley in the Contacts release a TiN barrier layer to address this problem. MICS process is the basic process: the completion of tungsten metal CMOS process, the deposition of 300 10-10nm low-temperature oxide (LTO), and then, low pressure chemical vapor deposition 200 10-10nm protection of the silicon nitride film has been produced CMOS circuits, micro-structure and corrosion End CMOS circuit contact hole, No. 1 layer deposition scene doped polysilicon (350 10-10), as CMOS circuits and micro-structure of interconnection lines, in the above deposition to a um PSG thick as a sacrificial layer thickness and deposition of 2 um polysilicon layer structure. No. 2 through another layer polysilicon deposition of a layer of 0.5 um PSG, as well as nitrogen environment in the 1000 rapid thermal annealing for 1 min as a structure to reduce stress polysilicon layer. Finally, the structure of graphics and polysilicon etching out its corrosion layer below the sacrifices (PSG) for the release of micro-structure.2.1.2 Other materials for the structure of the surface micro-machining technology integrationPolycrystalline silicon germanium polysilicon not only with the excellent mechanical properties similar, and, low temperature deposition compatible with the CMOS process, therefore, is being extensively studied. Developed at the University of Berkeley-based structural layer of silicon germanium technology and MICS technology similar. Major technological innovations: First, the protective layer using different materials, before 835 MICS process is the LPCVD silicon nitride, and now it is using a two-tier LTO and intermediate folder is not a stereotypical silicon (a-Si) as a CMOS circuit protective layer, in which the two-step deposition of a-Si, the first step in the deposition 450 ； step deposition in the 410 , this will not damage the temperature of aluminum metal CMOS circuit； Second, the low amylin plot structure as a temperature polysilicon layer of germanium materials, the low pressure chemical vapor deposition (LPCVD) temperature only 400 using rapid thermal annealing temperature of only 5.5 for 30 s. MICS and the temperature polysilicon deposition of more than 600 . From the above two points, we can see that the whole follow-up MEMS processing temperature does not exceed 450 , therefore, not of aluminum metal interconnect CMOS circuits have greatly affected.Aluminum used as a structural material will be a great success, the most successful is the Texas Instruments developed cryogenic surface micro-machining technology, and use this technology successfully produced digital micromirror device (DMD). Technical innovation in the use of sputtering performance as aluminum structural material, and using photoresist as a sacrificial layer, which makes low-temperature post-processing production has been below the SRAM cells were not damaged.Lead zirconate titanate (PZT) of the material has an excellent result piezoelectric properties, pyroelectric properties of ferroelectric properties and dielectric properties and is widely used in ferroelectric memory, as well as high-dielectric materials. At the same time, we can also use lead zirconate titanate piezoelectric effect produced micro-sensors and micro-actuators. PZT thin film silicon technology and integration technology compatible, such as the present based on the metal-organic chemical vapor deposition (OCVD) Methods PZT thin films temperature has been reduced to 430 to 75 , the temperature is lower, therefore, use of such materials as structural layer is a very hopeful and CMOS process integration.2.2 CMOS structure to the original layer to the structure of integrated MEMS technology2.2.1 Sacrifice aluminum micro-machining technologyIf CMOS metal compounds used for the expense of materials, there may be fully compatible with CMOS technology and surface micro-machining small art, this method is called sacrifice aluminum etching (sacrificial aluminum etching, SALE). In many CMOS process, use two layers of aluminum alloy by a metal layer. No. 1 as a sacrificial layer of metal was removed, can create metal dielectric compounds； Layer 2 and passivation of the metal component, 2-layer metal between two dielectric between appropriate structure, they could serve as a mirror electrodes, heat or electric resistance regulator. The basic process include: (1) the protection of electrical contacts are not connected etching (2) corrosion sacrifice aluminum layer； (3) removal rinsed Boundary structure inside the etching agent； (4)-drying bodies.2.2.2 Monocrystal silicon etching and metal activation method.Monomer silicon etching and metal activation method (single crystal reactiveetching and metallization, SCREAM) can be used for manufacturing, beam, the bridge structure, and even silicon can be used to create more complex structures. This approach starts at the End manufacture silicon CMOS circuits, first of all, a layer of coverage deposition contact hole silicon oxide, oxide layer to protect it from the back of CMOS circuits affected, and through reactive ion etching (RIE) of this graphics Oxide layer shielding layer； then RIE etching silicon trench, the depth of up to 10 um, silicon oxide thin film deposition down, and the level of coverage in the side surface. By reactive ion etching of the oxide surface level off due to a vertical surface to be protected, the second reactive ion etching silicon； Finally, the isotropic etch silicon, the release of the microstructure of a suspension, at the same time, etching contact hole oxides, and Sputtering metal, this layer of metal deposition to the aspect ratio of the beam into a capacitive elements with thick resist masking agent for the graphics mode of metal layers. As each step of SCREAM are below 300 under the temperature and, therefore, is compatible with CMOS circuits.2.2.3 Large aspect ratio of CMOS-MEMS TechnologyGamegle Melloa University and the development of CMOS-compatible dry etching method, which isotropic silicon etch applications have insulation film, CMOS dielectric and metal layers in this process, not only for the metal interconnect, but also as a micro-mechanical structure tail. Basic process: First, the standard CMOS process using three-metal process to achieve 0.5 upmN Well, secondly, metal layers 1 and 2 were used as electrical activity layer, and layer 3 as a micro-machining etching mask. Application of the compound CHF3/O2 reactive ion etching (RIE), the entire chip passivation layer to be removed, in the three-tier regional disconnect metal, CMOS laminated film has been etched to the basement, and above covered with Layer 3 CMOS metal thin film laminated retained intact； Finally, the use of SP6/O2 plasma etching in the micro-structural wall not under isotropic etch silicon substrate. Narrow insulating layer and conductive layer fused to create beams and bridges, such as: Comb drive the micro-structure.2.2.4 Processing CMOS-MEMS TechnologyMainly through the etching of silicon substrates, such as processing technology to form the necessary MEMS structure, the technology mainly to the University of Zurich-based. Can be viewed in a positive etching silicon substrate, but also from negative etching silicon substrate, using anisotropic etching (100) in the direction of the characteristics of the silicon etching could be positive not closed micro-structure, such as beams and support film , the choice of etching can be tetramethyl ammonium hydroxide solution (TMATH) or ethylene diamine solution (EDP). From what has been done through the back of the silicon wafer of silicon can be pitting the closure of the dielectric film, the need for a definition of additional patch mask the size of the commonly used candle is engraved on KOH. XeF2 dry etching using the post-CMOS technology has also made great development. XeP2 is an anisotropic etching of silicon, etching at high velocity, it is an inert gas xenon rare compounds. XeP2 neither IC insulating layer etching, etching aluminum or metal compounds, therefore, and CMOS compatible. After the appropriate regional design, connectivity and processing mask, opened in designated parts insulating layer, so that local exposure to silicon substrate etching agent. XeF2 because that is not etched ceramic, not plastic etching and thus suitable for CMOS integrated micro-processing system. In the use of this method can be completed with CMOS chip micro-etching mask institutions.3.Development Trend Monolithically integrated MEMS technology has been developing for more than 10 years, has been the rapid development has also seen the emergence of a MEMS manufacturing services organizations and enterprises, which will be some special organizations or directly from the IC manufacturers to provide MEMS processing. IC Microsystems representative of the direction of technology development organizations, including the United States and Europe TIMACMP MOSIS.Europractice； North Kaluona state Croons Integrated Microsystems Inc., in addition to providing the basic CMOS process, the body also provides micro-machining and surface emblem processing, LIGA process, as well as multi-user MEMS technology； the United States Sandia National Laboratory development of the multi-storey hyperplane polysilicon technology has been commercialized in Europe in the application-specific integrated circuit manufacturing technology research, including Austria Microsystems and Switzerlands EM Microelectronics. There are many special silicon-based sensor technology has also been finding out, for example, Germanys Luobaitebo Oxfam and the Norwegian SensoNor companies. Judging from the current situation, integrated MEMS technology will have the following trends: (1) post-CMOS integrated approach will continue to be the main future development of technology, and the existing laboratories have developed various post-CMOS single-chip integrated MEMS technology industry； (2) in the integrated MEMS system more complex integrated circuit including digital interfaces and microcontrollers, so that a more powerful, cheaper intelligent systems； (3) the development of CMOS chip packaging technology protection against environmental impacts, not only need to develop a system to integrate the MEMS package, but also need to adapt to the development of the single-chip package integrated MEMS technology.4.Concluding remarks Monolithic Integrated Intelligent MEMS sensor is the key to the development of IC industry is an important direction. Although various methods are some problems still exist, however, with its constant research and CMOS process compatibility problems will be all the solutions. In this paper, monolithic integration of MEMS technology to the requirements were discussed, and monolithic integration of various characteristics of MEMS technology, a process, at the same time, also gives future monolithic integration of MEMS technology development trend of the future.单片集成MEMS技术在过去的20年中，CMOS技术已成为集成电路主要制造工艺，制造成本下降的同时，成品率和产量也得到很大提高，COMS工艺将继续以增加集成度和减小特制尺寸向前发展。当今，CMOS集成工艺不仅被利用在集成电路设计上，而且，也被利用在很多微传感器和微执行器上，这样可以把微传感器与集成电路集成在一起，构成功能强大的智能传感器。随着微传感应用范围的不断扩大，对传感器的要求也越来越高，对未来微传感器的主要要求是：微型化和集成化；低功耗和低成本；高精度和长寿命；多功能和智能化。硅微机械和集成电路的一体化集成可以满足上述要求。目前，集成传感器的产品多 用 集成，单片集成的 很小。而 单片集成是 传感器智能化的 ，特 是单片集成MEMS传感器技术也是当今片上 片能 的 技术一。可 ，对 单片集成MEMS技术 行 以 目前已的 单片集成MEMS技术是 要的。单片集成MEMS技术的和的MEMS和CMOS同工currency1是 制造MEMS传感器和CMOS集成电路，“， 的片fifl， 在一同的上， 且， ，这样 ”的集成，这是的 。这 不产MEMS制造过 对CMOS电路的，同时，”产过 不。是， 过 和 ， 在高 应用时， 传 量下降， 且，fl发 产增加 产品的成本。为一 能 ， 降低制造成本，提 把MEMS 在和CMOS电路同一 上，也是产 与CMOS工艺 单片集成MEMS技术CMOSMEMS技术。这 对 的来 下：一， 能能得到很大的提高， 为电 和 可以 减小； ， 要的技术以减小传感器 的 ，而单片集成 要的技术对简单，以，降低传感器成本；三，单片集成传感器技术也是阵列传感器的 要，是克服阵列传感器与外围译码电路 瓶颈的一 效； 四，fl发单片集成MEMS产品 fl发 MEMS产品 的时间短，而且，fl发成本低。单片集成MEMS技术根据MEMS器件 与CMOS电路 加工顺序不同可以 为前CMOSpeCMOS、 CMOSntemeateCMOS“CMOSpostCMOS集成。postCMOS是在加工完CMOS电路的硅片上，通过一 附加MEMS微细加工技术以 单片集成MEMS ，目前，单片集成MEMS技术主要以这 为主。postCMOS主要 是MEMS加工工艺温度对前的CMOS电路 能产 ，更为严重的是“高温MEMS加工工艺温度与前CMOS工艺金属化不 。以目前研究最多的多硅currency1为结构层的MEMS为 ，使磷硅玻璃 密化退火温度为950，而使currency1为结构层多硅的应力退火温度则达到 050，这将使CMOS器件结深发迁移。特 是800时浅结器件的结深迁移 器件的 能。另一， 用 规铝金属化工艺时，当温度达到400450时，CMOS电路可靠 将受到严重的 。以上可以看 ： 何克服“高温MEMS微结构加工温度对前的已加工完的CMOS电路 是 单片集成MEMS 在。目前，国际上 这 基本是通过3式： 一 是以 熔金属化 代替铝金属化 ， ，伯克利大学的以钨代替铝金属 案，这样提高 忍“续加工MEMS 的高温； 式是通过寻找低制currency1温度且机械 能良的材料代替多硅currency1为结构层材料； 三 式是利用CMOS本身已 结构层currency1为MEMS结构层。peCMOS集成是先制造MEMS结构“制造CMOS电路，这 集成CMOS技术虽克服postCMOS中MEMS高温工艺对CMOS电路的， 存在垂直的微结构，以，存在传感器与电路 台阶覆盖 ，而且，在CMOS电路工艺过 中对微结构的保护也是一要考虑的 。甚至已化微调的CMOS工艺流 ， ：栅氧化可能被重掺的结构层 。另外，MEMS工艺过 中不能 任何的金属其他的材料， 压电材料聚 物等，使得这 只适 一 特殊应用。ntemeateCMOS是在CMOS电路产过 中插入一 MEMS微细加工工艺来 单片集成MEMS的。这 已很成熟， 已 很多商品化产品，也是研究最早一 单片集成，是 peCMOS和postCMOS存在 效，是， 要对 的标准CMOSBCMOS工艺 行较大的 ， ，这 的使用 一 制。2 单片集成MEMS的主要技术 目前，单片集成MEMS技术主要以postCMOS技术为主，通过一 列的与CMOS工艺 的 微细加工和体加工 单片集成MEMS。 可 为2 ：一 是在CMOS结构层上 一层结构层的微加工；另一 是直 以CMOS 的结构层currency1为MEMS结构层的微加工。2 的结构材料currency1MEMS结构的集成技术2 多硅currency1为结构层的集成 微细加工技术这 工艺 型代 是伯克利大学fl发 集成CMOS与MEMS工艺mo a nte aton o CMOS t m ost t es，M CS，这 是以多硅为微结构层，磷硅玻璃 S currency1为 层的 微细加工技术。 用 熔金属钨的金属化 代替铝金属化 以 受“的产多硅微结构 要的高温，是，在 00时，钨 与硅 成 应，伯克利大学是通过在 上一层层来 这一 的。M CS工艺基本流 是：完成钨金属化的CMOS工艺“， 300 0 0nm低温氧化物O，“，低压化学currency1 200 0 0nm的化硅“保护已产的CMOS电路，完微结构与CMOS电路的 “， 层 fi掺多硅350 0 0currency1为CMOS电路与微结构的 ， 在上 mfl的 S currency1为 层以 fl度为2 m多硅结构层。通过在 2层多硅上 一层0 5 m的 S ，以 在currency1 下的 000退火 mn来降低currency1为结构层的多硅应力。最“，多硅结构 以 其下的 层 S 以微结构。2 2 以其他材料currency1结构层集成 微细加工技术多硅不仅 与多硅的良机械 能，而且， 温度低与CMOS工艺 ，以，目前被”研究。伯克利大学fl发的基 硅结构层的工艺与M CS工艺基本。主要技术 ： 一，保护层 用不同的材料，以前M CS工艺 用835的 C 化硅，而 在则是 用层O和中间一层不型硅aScurrency1为CMOS电路保护层，其中，aS ， 一 在450； 则在4 0，这样温度是不铝金属化CMOS电路； ， 用低