段成华老师《数字集成系统设计》笔记整理v101.docx

Digital Integrate Circuit Design Class NoteVersion 1.0.1Announcement 首先感谢学长（or学姐）的付出，只有亲身去做的时候才感到整理此笔记的工作量真心很大。同时，也感谢段老师在授课过程中的风趣、责任心。在1.0.0版本上对笔记进行了更正与补充。由于个人水平的问题，笔记中难免有错误疏漏，望大家见谅。希望有人继续对这份笔记进行补充、修正。由于课程变化的原因，在我这届，段老师并没有讲第六章。保留了上版本中的第六章供大家参考学习。学习资料供大家自由分享。转载的过程中，本着“爱人如己”的原则，请不要在百度文库之类的地方索要积分。最后，将自己整理笔记的劳动献给勇敢的主内姐妹小郭子，虽然她肯定会对笔记所讲的东西发昏。Referance书【1】：James R. Armstrong, F. Gail Gray . VHDL设计表示和综合（原书第2版）. 李宗伯，王蓉晖，王蕾等译.机械工业出版社.2002.书【2】：阎石.数字电路技术基础（第5版）.高等教育出版社.2004.Teacher段成华：ContentCH1 Design Abstraction and RepresentationCH2 Digital Logic Device and ArrayCH3 Basic VHDL ModelingCH4 Combinational Synchronous LogicCH5 FSM(finite states machine) DesignCH6 Algorithmic Model EDA Tools1. Xilinx ISE project Navigator2. Modelsim（软件可以找助教拷）Chapter 1 Design Abstraction and Representation1.1 The Problem of IC. Design and the Solutions1.1.1 A History Perspective(1) First IC.(1958) Jack Kilby (19232005)德州电器TTL逻辑80年代，2000年 Nobel Price.1.1.2 IC. Design Complexity(1) ITRS(International Technology Roadmap for Semiconductor)(2)工艺参数：年份特征尺寸(nm)门极电压(v)数量备注19953503.310M20011301.2100M1亿2010450.61B10亿2016224.2100B(3) ComplexityFeature Size(特征尺寸)：Gate-equivalent Corresponds to a 2 input NAND gate做一个与非门的面积法则 roughly half the length of the small transistor.Reliably(可信性) variability(变化性)(4)Solution解决复杂性的方案A. Design Abstraction 设计抽象B. Formal Representation 正式表达1.2 Design Representation and Hardware Description Language1.2.1 Y-chart 1983 Daniel D. Gajski(1)Abstract level 1System level系统级2Chip level芯片级3Register-Transfer level寄存器级4Logic gate level逻辑门级5Circuit level电路级图1 Y图表示结构表示功能表示几何表示处理器内存交换寄存器转化电路系统算法布尔表达板图规划若干单元遮罩(mask)几何Design Representation: refers to a way to describe a chip in the domains of Behavioral, Structural and Geometrical.(2)Main Components of Y-chart rep.a) Behavioral rep. (BR, BD)Def.: Representing a design as a black box and describes its output in term of its input and time, l indicating no geometrical and structural information, l taking the forms of textual, mathematic and algorithmic.Example: XOR:A=AB+AB no any geometric information to some extent, no structure information.b) Structure Rep. (SD, SR):Def.: A black box is represented as a set of components and connects (interconnection).l It may be generated by mapping functional representation into a set of components and connection.l no physical information is contained.Example:(3)Geometrical Rep.(GR, GD)a) Def.: Specifying size (height and width) of each components; the position and interconnected on silicon die.Geometrical Shapes represent regions of 1) Diffusion2) Polysilicon and3) Metal on silicon waferIt includes MASK information.1.2.2 Subtype of Behavioral Description1. Algorithmic description Conducted through the algorithmic path of the component2. Dataflow description Matching data dependency in real implementation.1.2.3 Hardware Design language (HDL)An example of model HDL: 1970s SpecificationPort inv (in)out(1) Nfet out in vss(2) Pfet out in vdd/end高级语言低级语言创建时Delay问题并发性A VHDL examplei1+i2=o;ENTITY OR2 ISPort(i1,i2:in bit; o out bit); END OR2ARCHITECTURE D OF OR2 ISBEGAINo = i1 or i2ENDOne HDLl For synthesis 生成硬件l For simulation 仿真l Fast vector 测试矢量功能描述有延时，行为描述无延时1.3 Structure Design 1.3.1 The Abstraction Hierarchy(1) Abstraction hierarchy: A set of interrelation representation levels that allow a system to be represented in varying amounts of detailThe hierarchy of IC design:BDSDHigh levelSystem-levelFunctional or Behavioral specificationComputer SOCAlgorithmic-level (chip-level)Algorithm PMG(Process Model Graph)CPU DSP RAMRTLData flow graphFSMRegister ALU MUXLogic gates levelBoolean equationK-mapLogic Gates FF(flip flop)Circuit levelDiff equationTransistor R/C/L(2) Computational step: Data process time时钟周期1.3.2 Design and implementation Process图1 Y图表示行为表示结构表示几何表示Optimization优化Generation生成Extraction抽取refinementsabstractionAnalysisSynthesisRelationship Between Design(Logic) and Implementation(physical)SystemChipRTLGateCircuitLayoutBehaviorStructurePCB设计方向PCB 有芯片直接焊制在板子上.FPGA(Field Program Gate Array)现场可编程门阵列.Design CyclesSystemChipRTLGateCircuitLayoutBehaviorStructurePCBPLD (CPLD, FPGA)VLSI (ASIC)设计主要的RTLFull custom designSystemChipRTLGateCircuitLayoutBehaviorStructureGeometricEnglishNatural language综合AlgorithmDataflowLogicCircuitGeometric ShapeBehavior综合Logic综合physical综合layout综合Synthesis: The process of transforming one representation in the design abstraction into another representation.Synthesis=translation + optimisticDesign cycles: a series of synthesis steps.System level synthesis: mapping a task-level specification(系统级的规范) on a heterogonous hardware/software architecture.physical synthesis 物理综合RTLlayout 从行为域到几何域1.3.3 IPs and Y-chart repIP: Intellectual Property 知识产权，表示预定义组件(predefine module)l Each abstraction level needs a database of componentsl Each component has three model(B,G,S)a) Behavioral model (soft IP core)b) Structural model (hard IP core)c) Physical layout model (fixed IP core)Structure design decompositionKey QuestionModel Size 50k500k(门数)How many clocks? One of each moduleDesign TreeFull design treePartial design treeDesign window: a ranges of level worked atDigital Design SpaceCostSpeed (performance)Power dissipation损耗1.4 Design Flow1.4.1 FPGA/CPLD Design flowTest VectorSpecificationHDLFunction simulationSynthesisSimulationPlace & Route (P&R)Static timing veificationPro typeIn system testingproductionDesign entity功能仿真实际的行为仿真综合，之后就有了门级的网表真正的功能仿真静态的时序监管post-sim1.4.2 ASIC design flowSpecificationHDLFunction simulationSynthesisSimulationplacement & Route Static timing verificationSign offIn system testingproductionDesign entity功能仿真实际的行为仿真综合，之后就有了门级的网表真正的功能仿真静态的时序监管post-simF type签合同开卖4 week read time1.4.3 SoC Design flowRequirementAlgorithm Development System level designEmbedding software developmentHardware developmentCor-verificationPhysical hardware/softwareRTL CreationRTL simRTL synthesisR&PFunctional sim(Gate)SDF Gate simVHDL SDF1.5 Design ToolsHigh level system-level, chip-level.Classification:1 design entry2 logic design3 physical design4 verification5 high level synthesisChapter 2 Digital Logic Devices2.1 Basic Concept2.1.1 Categories of Digital LogicCostTimeSPPLGASCFCSP:Standard Products PL:Programmable Logic GA:Gate Array SC:Standard Cell FC:Full Custom2.1.2 Electrical Parameters of Digital ICLogic DeviceInputOutputVDDGNDClockIIH IILIOH IOLVIH VILVOH VOLElectrical Parameters:1. Clock2. Voltage3. CurrentIOH IOL IO(off) IOZ IOS IIH IILOutput States : highlowoff3-stateshort-circuitDelay: Tpd: Propagation delay2.2 Common Used General Logic Devices2.2.1 Basic Logic gatesInverter: NAND, NOR, XOR, NXOR2.2.2 D-flip-flopstsuI : Setup timethd : Hold timetcoI : C时钟，O输出2.2.3 Bi-stable latch不对称电路会带来竞争，产生毛刺如右图2.2.4 Binary Counter2.2.5 Synchronies Counter2.2.6 2-to-4 line decoder2 to 4 decoderGABY0Y1Y2Y32.2.7 Multiplexer (MUX)多路开关C0Y100C1Y101C2Y110C3Y111Y1=ABC1+ABC2+ABC3+ABC4多布尔述如下：Fx1,x2,xn=x1F0,x2,xn+x1F(1,x2,xn)2.2.8 Bus transistor2.3 Programmable Logic Device2.3.1 PAL可编程逻辑阵列(Programmable Array Logic)书【2】page 392(1) Basic PLA ArchitectureInputnInputlogicnPTsnANDArrayORArrayPTsnOutputLogicnOutputn(2) PAL Notatona) AND arrayb) PAL Architecture 书【2】P392c) PAL Output structureActive LOW Bi-dir output 书【2】p394 图8.3.4 Active High 书上没有Registered output 书【2】p395 图8.3.6XOR register output 书【2】p396 图.2 GAL通用阵列逻辑(Generic Array Logic)书【2】P402Output logic Macro Cell(OLMC)书【2】P405 图8.4.4 注意该图有错误，对照老师作业2中所留图片2.4 Complex Programmable Device2.4.1 Basic Concept1. Architecture of PLD Components + InterconnectionXlinx CPLD Architecture1) Basic interconnect methodology2) Logic block3) Logic allocation method4) Timing model of the device5)2. Interconnect Matrix of CPLD 1) Cross Point Switch 2) MUX-Based Interconnect 3) XPLA3 ZIA (Zero power Interconnect Array) 老师只是提了一下，具体结构不详3.Logic Block (Architecture)（会有三四个图，我所记的笔记不是很详细，课上记老师的板书吧，见谅）（第一个图在这里画不下）4.Product Term Allocationl PT SharingA. PAL Architecture AND: ProgrammableOR: FixedB. PLA (XPLA3) AND: ProgrammableOR: Programmable5.Macro-Cell(这里有两个图)2.4.2 I/O Timing Model1. I/O Cell 2. Timing Model 1) Using combinational logic2) Using Register Logic2.5 FPGA1. FPGA architecture PSM: Programmable Switch Matrix CLB: Configurable Logic Block PIP: Programmable Inter-connect Point2. Xilinx Spartan CLB 1) MUX-Based Logic 2) Look-up-table Based logicChapter 3 Basic VHDL Modeling Technique3.1 Introduction3.1.1 Significance1) Process Control, Standardization, Risk Control.2) Automation EDA：Synthesis/Simulation3) VLSI Testing3.1.2 Standardsl 1979s: initial definitionl Late 1970s:VHDL projectionl 1987: ieee std VHDL 1164 releasedl 1993: ieee std VHDL 1076 releasedl 2001: ieee std VHDL 1076 ra released4-bitABIf A=B then Equal to 13.2 Design Entity3.2.1 4-bit Equality ComponentsDesign case1) RTL schematic design (right figure)2) VHDL Design (Dataflow Model)library IEEE;use IEEE.STD_LOGIC_1164.ALL; -引入库use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY eqcompf IS -定义实体PORT(a:IN BIT_VECTOR(3 DOWNTO 0);b：IN BIT_VECTOR(3 DOWNTO 0);Equals: OUT BIT);END eqcompf;ARCHITECTURE dataflow OF eqcompf -结构体内为并发语句，写入进程内为顺序BEGAIN -语句。Equals=1 when (a=b)Else 0;END dataflow;3.2.2 Design Entity ConceptThe design entity is the primary hardware abstraction in VHDL. It is defined by an entity declaration together with a corresponding architecture body.Entity:l Defines the static characteristic of hardware including its range and interface.Interface: consistence, variable, signal, filel Represents an entity system, a circuits board chip and a logic gatel Declare all in and out portsArchitecture body:l Define the dynamic declarations of hardware (behavior)l Multi architecture can be defined of the same entityl Define styles (types)3.2.3 Entity declaration1) BNF (Backs-new format) of entity def.ENTITY entity name IS Port(signal identifier:mode(in/out/buffer)signal type; );END entityentity name;a) portsl Each I/O signal in entity declaration is called a portl A port is a data object and it can be assigned value or used in stalementb) Mode: declare the direction of data transfer (in/out/inout/buffer).buffer设定信号的输入输出c) Type(signal port)Boolean/bit/integer: support by ieee.1076,1993Std_logic: ieee.1164,1987U: unsolved(resolution)3.2.4 Architecture Definition1) BNF：ARCHITACTURE arch. name OF entity name IStype declaration(signal def./ constant def./components def./alice def./attri. spec./subpro body)BEGAIN process statementEND arch. name2)examplea) type def.TYPE BIT IS (0,1);TYPE STATE_TYPE IS (st0,st1,st2);b) signal def.SIGNAL static : static typeExample:SIGNAL x：BIT;d) constant def.CONSTANT zi : STD_LOGIC_VECTOR(7 DOWNTO 0):=”00000000”;e) components def.COMPONETS AND2 PORT(ij: IN STD_LOGIC; k:BUFFER STD_LOGIC);f) alices dealSINGNAL addr: STD_LOGIC_VECTOR(31 DOWNTO 0);ALIES TO top_addr: STD_LOGIC_VECTOR(3 DOWNTO 0 ) IS addr(31 DOWNTO 28);g) attribute specTYPE CONST IS INTEGRATE RANGE(0 TO 27);CONST LEFT(=0);h) Sub program bodyFUNCTION majority (a,b,c: BIT) RETURN BIT ISBEGAIN RETURN (a AND b) OR ( a AND c) OR (b AND c );END majority;3.3 Design Description Style3.3.1 Behavior Description (BD)comp: PROCESS(a,b) 敏感表BEGAIN IF a=b THENequal=1; ELSIFequal=0; END IF;End compFeature of BD(1) BD is conduct according to algorithm path;(2) BD is often one kind of high level description;(3) BD includes one or more process within arch. Body;(4) In a process, sequential statements are used.(5) The order of the sequential statements in a process is important.ARCHITECTUREBEGAIN P1 进程内顺序执行 - P2 -进程间并发执行P3 -END3.3.2 Dataflow Description (DD).ARCHITECTURE bool OF eqcomp ISBEGAIN Equal= NOT (a(0) XOR b(0)AND NOT (a(0) XOR b(0)AND NOT (a(0) XOR b(0)AND NOT (a(0) XOR b(0);END bool;Feature of Data flow Description:l DD use concurrent signal assignment statements instead of sequential or process statements;l The order of the statements has no effect on the logic function;l DD implies some structural information.3.3.3 Structure Description ARCHITECTURE struct OF eqcomp4 ISSIGNAL x: STD_LOGIC_VECTOR(0 TO 3);BEGAIN U0: XOR2 port map(x(0),a(0),b(0);U1: XOR2 port map(x(1),a(1),b(1);U2: XOR2 port map(x(2),a(2),b(2);U3: XOR2 port map(x(3),a(3),b(3);U4: XOR2 port map(x(4),a(4),b(4);END struct;ENTITY eqcomp4 IS END;ENTITY XOR2 IS PORT(d0,d1:IN BIT; q0:OUT BIT);END XOR2ARCHITECTURE XOR2 ISBEGAINEND XOR2;ARCHITECTURE struct OF eqcomp4 IS COMPONENT XOR2;-实体之前写入lib说明，否则放于最后容易出错。Feature of SD(1) SD calls components in Lib using USE dease and gets the in structural components.(2) Concurrent statements are used.(3) If consistent of net list（这里没有记录完整） 3.3.4 Comparison of Design Description StylesDifferent descriptions style lead to different implements with different sources.(1) redundant logic 多余逻辑(2) Inefficiency of optimizing device resources(3) General and render-specific componentsGeneral(BD): portability;Render specific (SD): non portability.3.3.5 Sequential Statement Statement that execute in the sequence are called sequential statement.(1) IF THEN ELSIF ELSEExample:IF count = “00” then a= b;ELSIF count = “10” then a= c;ELSE a a a a 0) loopcount := count+1;result= result + data_in;END My_lOOP;3.3.6 Sequential Statements(IEEE CRM 2000) Sequential statements execute in the order in which they appear.3.3.7 Concurrent Statements(J.R.Armstrong) Statements that can execute simultaneously are called concurrent statement.(IEEE CRM 2000) Concurrent statements execute asynchronously with respect to each other.(1) Boolean equationW=a OR b OR c(2) WhenelseY= j WHEN state=idles ELSEk WHEN state=firsts ELSEm WHEN OTHERS;(3) WITHE SELECT WHEN(4) Process statement BNF:process label:PROCESS(sensitivity list)type declaration/constant declaration/ variable declaration/sub program declaration/alias declarationBEGAIN sequential statementsEND PROCESS; at the beginning execute one time;signal in SL change then execute process.3.4 Modeling for Synthesis and SimulationQ: what are the differences between synthesis and simulation model?l Checking the source code to see that the correct set is usedl Syntactic(语法):a parser;l Semantic(语义): typical semantic: a) Declarationsb) Type checking3.4.1 Model Delay and Concurrency1. Propagation Delay(1) Delayed Signal AssignmentAS= X* Y AFTER 2ns;BS=AS+Z AFTER 2ns(2) Instantaneous variable assignmentAV:= X+Y;BV:=AV+Z;BS=BV;initialt1t1+2nst1+4nst1+6nsSignalX14553Y22232AS2281015Z03222BS2251012VariableX14553Y22232AS2810156Z03222BS21112178 2. Process, delay and concurrencyLogic block1Logic block2Logic block3Input1Input2output3Conclusion: The change in signal x at time t1 has its effect on AS at time t1+ and BS at t1+2. These concurrent signal assignments behave in a manner similar to that concurrent by finite delay due to build in delay. Concurrency=process+delay 3.4.2 Signal Assignment Execution1. Sequential signal assignmentl Executed in the order written.2. Concurrent signal assignmentl Assuming an implied SLl Executing simultaneously3. Process statement execution1) Process with SL(敏感表)l One process case:-Execute once at the beginning of simulation.-Only when a signal changes its value.l Multi process case:-Not be executed in the order, but instead- Executed only when a signal experience an event2) Process without SLP1:PROCESSBEGIN X=a AND b AND c;END PROCESS;P2:PROCESSBEGIN X=a AND b AND c; WAIT ON a b c;-产生测试矢量，不能综合，放于进程末尾，编译器承认END PROCESS; 3) Process with incomplete SLP4:PROCESS(a,b)BEGINP3:PROCESS(a,b,c)综合会警告，仿真不会报错BEGINY=a AND b;END PROCESS;END PROCESS;3.4.3 Signal Driver 信号的推动性PROCESS(x,y,z)BEGIN AS=x*y; BS=AS + z;END PROCESS;Definition(signal driver) if a process contains one or more signal assignments