AMBA APB study review.docx

AMBA APB Summary1. AMBA APB2/APB3/APB4区别1) APB2: basic timing and function2) Compare to APB2, APB3 adds:PREADY: wait states, to extend an APB transferPSLVERR: to indicate the failure of a transfer(, cannot write data or no valid read data, not necessary)3) Compare to APB3, APB4 adds:PPROT2:0: protection typePSTRB3:0: write strobe, indicate which byte contains valid wdata(must be driven all low when read transfer)2. AMBA APB2/APB3/APB4共同点1) The basic timing is based on APB2, when PREADY is tied HIGH, APB3/APB4 becomes APB2, and APB2 slave can connect directly to APB3/APB4 without change.AMBA 2.0 APB1. Operating status*SETUP & ENABLE state both only last for one cycle, that is each transfer last only two cycles2. basic timing*PSELxx, PADDR, PWDATA, PWRITE must keep constant during the transfer change from SETUP to ENABLE state*PRDATA just need to provide valid data at the last cycle for transfer.3. APB Bridge*function: converts system bus transfers into APB transfers and performs the following functionsLatchs the address and holds it valid throughout the transferDecode the address and generate PSELxDrives the data onto the APB for a write transferDrives the APB data onto the system bus for a read transferGenerate PENABLE for the transfer4. AHB to APB Timinga) write transferb) read transferc) notes*write transfer need two cycles to load the first address, but read just need one. The reason is write transfer need one cycle two send wdata after address, while APB bridge need load address & wdata simultaneously, so it has to wait the wdata loaded, thus need two cycles to load first addr; read transfer doesnt need data, it just need to load addr, so one cycle is enough.*the above transfer timing is the situation that has the fastest transfer type as each transfer need two cycles without IDLE, addr2 is registered in advance, this is realized by using two register and AHB & APB has the same clock. In reality, APB may not have same clock as AHB, and we may need a fifo(or something) with greater depth to register the untreated address.AMBA 3.0 APB1. Operating status*the transfer is similar to APB2, the difference is the ACCESS state may not last only one cycle with the PREADY, when PREADY=LOW, it extend the transfer*Timing*the PSEL, PWRITE, PADDR, PWDATA must keep constant during the whole transfer, while PRDATA just need to be valid when the PREADY/PSEL/PENABLE are all HIGH2. PREADYDuring the ACCESS state, when PREADY=LOW, it extend the transfer until PREADY=HIGH, the ACCESS state can last more than one cycle.PREADY can take any value when PENABLE=LOW, this make is easy for a APB2 slave connect APB3 Bridge directly through tie PREADY=HIGH3. PSLEVRR MappingPSLEVRR is only considered valid during the last cycle of transfer, that is when PREADY/PSEL/PENABLE are all HIGHFrom AXI to APB mapping: RRESP/BRESP = SLVERR, mapping PSLEVRR to RRESP1 for reads and BRESP1 for writeFrom AHB to APB mapping: HRESP = ERROR, mapping PSLEVRR to HRESP0AMBA4.0 APB1. Operating statusSame as APB32. PPROT2:0Protection typePPROT0: 0 normal access 1 privileged accessPPROT1: 0 secure access 1 non-secure accessPPROT2: 0 data access 1 instruction access3. PSTRB3:0Write strobe signal, enable Sparse data transfer. Each bit correspond to one byte of the wdata bus, when PSTRBn = HIGH, it indicate the byte data contains valid information.For read transfer, the bus master must drive all bits of PSTRB LOW !4. signalssignalsourcesignalSourcePCLKClock sourcePPROTSystem bus equivalentPRESETnSystem