硬件描述语言HDL的现状与发展.doc

HDLEDAASICFPGA(high-level-design)90%ASICFPGAHDL2020802080VHDLVerilog HDLIEEEFPGASuperlogSystemCCynlib C+EDA1 HDLVHDLSuperlogVerilogSystemCCynlib C+C LevelHDLC/C+2001HDL?23SystemCCynlibC LevelSuperlogVerilog20John Cooley5VerilogSystemCSoCCVerilogCynlib C+SuperlogSuperlogVerilogVerilog HDL-A2 HDL2.1 VHDL1980VHDL1987IEEEInstitute of Electrical and Electro- nics EngineersVHDLIEEE VHDL1076/B1987IEEE 1076-1987VHDL1993VHDL-93VHDL4VHDL1995VHDLVHDLVerilog HDLVerilogVDHLOVIVIVHDLVerilog HDLOVIVHDLVerilog2.2 Verilog HDLVerilog HDL1983GDAGateWay Design AutomationPhil MoorbyPhil MoorbyVerilog-XLCadence19841985Phil MoorbyVerilog-XL1986Verilog HDLXLVerilog-XLVerilog HDL1989CadenceGDAVerilog HDLCadence1990CadenceVerilog HDLOVIOpen Verilog InternationalVerilog HDLVerilog HDLIEEE1995Verilog HDLIEEEVerilog HDL 1364-19952001Verilog HDL 1364-2001Verilog HDL-AVerilog2.3 SuperlogCC+Java?SuperlogVerilogPhil MoorbyPeter FlakeCo-Design AutomationEDAVerilog1999Co-DesignSUPERLOGTMSYSTEMSIMTMSYSTEMEXTM2001Co-DesignAccelleraSUPERLOGESSVerilogRTLEDA15SuperlogSuperlogITEDACo-DesignSynopsys2.4 SystemCSoCSoC SystemCSynopsysCoWare199992740EDAIPSystemCCadence2001SystemCSystemC199990.91.01.12001102.03 HDL3.1 SystemCSystemCC+1SystemCFIFO1SystemCANSI C+SystemC3.2 SuperlogSuperlogVerilogC2 Verilog 95Verilog 2KSuperlogVerilog HDLVerilog 2K CC+SuperlogCC+ SuperlogESSESS SuperlogCo- Design AutomationSYSTEMSIMTMSYSTEMEXTMEDA3.3 VerilogVHDL4 system algorithm RTLRegister Transfer LevelRTL gate-level switch-levelIP VHDLCVerilogVHDLVerilogSOC SuperlogVerilog HDLSuperlogSYSTEMSIMTMSYSTEMEXTM SystemCSystemCVerilog HDLANSI C+ 5 0.25m 0.18m0.13m90nm0.13m90%2GHz0.13m EDA EDA ALFEDA SoC5 ITASICEDASynopsys