16位乘法器学习笔记(Verilog语言源程序+仿真程序).doc

LCD1602显示源程序如下：module lcd1602(input clk, /60M input rst_n, output lcd_p, /Backlight Source + lcd屏幕背光 output lcd_n, /Backlight Source - output reg lcd_rs, /0:write order; 1:write data output lcd_rw, /0:write data; 1:read data output reg lcd_en, /negedge 在lcd_en下降沿需保证数据有效 output reg 7:0 lcd_data); mux16 mul(.rst_n(rst_n),.clk(clk),.start(start),.ain(data0),.bin(data1),.yout(data2),.done(done);/端口名称关联 /-lcd1602 order-parameter Mode_Set = 8h31, /功能设置， Cursor_Set = 8h0c, /光标设置 Address_Set = 8h06, /输入模式设置 Clear_Set = 8h01; /清屏设置 /*LCD1602 Display Data*/ wire 7:0 data_r0,data_r1,data_r2; /乘数、被乘数wire 15:0data0,data1; /结果显示wire 31:0data2; wire 7:0 addr; /write addresswire start,done; assign data_r0 = 8h30 + data07:0 ; / 8h30在LCD1602上显示值为0。 assign data_r1 = 8h30 + data17:0 ;assign data_r2 = 8h30 + data27:0;/-address-assign addr = 8h80; /*LCD1602 Driver*/ /-lcd1602 clk_en-reg 31:0 cnt;reg lcd_clk_en;always (posedge clk or negedge rst_n) begin if(!rst_n) begin cnt = 1b0; lcd_clk_en = 1b0; end else if(cnt = 32h24999) /600us begin lcd_clk_en = 1b1; cnt = 1b0; end else begin cnt = cnt + 1b1; lcd_clk_en = 1b0; endend /-lcd1602 display state-reg 6:0 state;always(posedge clk or negedge rst_n)begin if(!rst_n) begin state = 1b0; lcd_rs = 1b0; lcd_en = 1b0; lcd_data = 1b0; end else if(lcd_clk_en) begin case(state) /-init_state- 6d0: begin lcd_rs = 1b0; lcd_en = 1b1; lcd_data = Mode_Set; /进入功能设置模式，“31”：数据总线8位，显示一行。6*7点阵/每字符 state = state + 1d1; end 6d1: begin lcd_en = 1b0; /lcd_en变低电平，使led_en出现下降沿 state = state + 1d1; end 6d2: begin lcd_rs = 1b0; lcd_en = 1b1; lcd_data = Cursor_Set;/光标设置：光标右移一格，且AC值加1. state = state + 1d1; end 6d3: begin lcd_en = 1b0; state = state + 1d1; end 6d4: begin lcd_rs = 1b0; lcd_en = 1b1; lcd_data = Address_Set;/模式设置：写入新数据后光标右移，AC自增1 state = state + 1d1; end 6d5: begin lcd_en = 1b0; state = state + 1d1; end 6d6: begin lcd_rs = 1b0; lcd_en = 1b1; lcd_data = Clear_Set;/清屏操作：0x01 state = state + 1d1; end 6d7: begin lcd_en = 1b0; state = state + 1d1; end /-work state- 6d8: begin lcd_rs = 1b0; lcd_en = 1b1; lcd_data = addr; /write addr state = state + 1d1; end 6d9: begin lcd_en = 1b0; state = state + 1d1; end 6d10: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = R; /write data state = state + 1d1; end 6d11: begin lcd_en = 1b0; state = state + 1d1; end 6d12: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = E; /write data state = state + 1d1; end 6d13: begin lcd_en = 1b0; state = state + 1d1; end 6d14: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = S; /write data state = state + 1d1; end 6d15: begin lcd_en = 1b0; state = state + 1d1; end 6d16: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = :; /write data state = state + 1d1; end 6d17: begin lcd_en = 1b0; state = state + 1d1; end 6d18: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = data_r1; /write data: tens digit state = state + 1d1; end 6d19: begin lcd_en = 1b0; state = state + 1d1; end 6d20: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = *; state = state + 1d1; end 6d21: begin lcd_en = 1b0;state = state + 1d1; end 6d22: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = data_r0; /write data: single digit state = state + 1d1; end 6d23: begin lcd_en = 1b0; state = state + 1d1; end6d24: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = =; /write data: single digit state = state + 1d1; end 6d25: begin lcd_en = 1b0; state = state + 1d1; end 6d26: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = data_r2; /write data: single digit state = state + 1d1; end 6d27: begin lcd_en = 1b0; state = state + 1d1; end 6d28: begin lcd_rs = 1b1; lcd_en = 1b1; lcd_data = .; /write data: single digit state = state + 1d1; end 6d29: begin lcd_en = 1b0; state = 6d8; end default: state = 6bxxxxxx; endcase endend assign lcd_rw =1b0; /only write /-backlight driver-assign lcd_n = 1b0;assign lcd_p = 1b1; Endmodule16位乘法器源程序如下：timescale 1ns / 1psmodule mux16(clk,rst_n,start,ain,bin,yout,done);input clk;/芯片的时钟信号。input rst_n;/低电平复位、清零信号。定义为0表示芯片复位；定义为1表示复位信号无效。input start; /芯片使能信号。定义为0表示信号无效；定义为1表示芯片读入输入管脚得乘数和被乘数，并将 /乘积复位清零。input15:0 ain;/输入a（被乘数），其数据位宽为16bit.input15:0 bin;/输入b（乘数），其数据位宽为16bit.output31:0 yout;/乘积输出，其数据位宽为32bit.output done;/芯片输出标志信号。定义为1表示乘法运算完成.reg15:0 areg;/乘数a寄存器reg15:0 breg;/乘数b寄存器reg31:0 yout_r;/乘积寄存器reg done_r;reg4:0 i;/移位次数寄存器/-/数据位控制always (posedge clk or negedge rst_n)if(!rst_n) i = 5d0;else if(start & i 5d17) i = i+1b1; else if(!start) i = 5d0;/-/乘法运算完成标志信号产生always (posedge clk or negedge rst_n)if(!rst_n) done_r = 1b0;else if(i = 5d16) done_r = 1b1;/乘法运算完成标志else if(i = 5d17) done_r = 1b0;/标志位撤销assign done = done_r;/-/专用寄存器进行移位累加运算always (posedge clk or negedge rst_n) beginif(!rst_n) begin areg = 16h0003;breg = 16h0003;yout_r = 32h00000000;endelse if(start) begin/启动运算if(i = 5d0) begin/锁存乘数、被乘数areg =ain;breg 5d0 & i 5d16) beginif(aregi-1) yout_r = 1b0,yout30:15+breg,yout_r14:1;/累加并移位else yout_r 1;/移位不累加endelse if(i = 5d16 & areg15) yout_r31:16 5d0 & i 5d16) begin if(aregi-1) yout_r = 1b0,yout30:15+breg,yout_r14:1;/累加并移位 else yout_r 1;/移位不累加 end else if(i = 5d16 & areg15) yout_r31:16 = yout_r31:16+breg;/累加不移位对于 if(aregi-1) yout_r = 1b0,yout30:15+breg,yout_r14:1;此句说明如下：（1） 、二进制中16位加上16位结果为17位（2） 、areg0为1时，第一次只是加并不右移，后面aregi-1再次为 1时执行累加并右移命令。右移实现通过拼接强制最高位（即第32位）为0实现的。（3）、 else if(i = 5d16 & areg15) yout_r31:16 = yout_r31:16+breg;/累加不移位对于此语句当areg15即最高位为1且i=16时只进行累加，再次应注意最高位（即第32位）的变化。3、 第2条的思想是基于如下二进制算法实现的： 1101X 1011 1101 11010000 1101 100 01 0114、 尝试结果在LCD1602上面显示出来： （1）