基于VHDL的八路彩灯控制器.doc

沈阳理工大学课程设计专用纸NO.15目录1.任务需求22. 总体设计22.1 各个花样的状态图22.2总体框图43. 模块设计43.1分频器模块43.2花样一模块53.3花样二模块63.4花样三模块83.5顶层设计104. 仿真图114.1分频器仿真波形114.2花样一仿真波形114.3花样二仿真波形124.4花样三仿真波形134.5总体仿真波形135.心得体会146.参考文献151.任务需求现今生活中，市场上未能吸取顾客的注意，高出各式各样的方法，其中彩灯的装饰便是其中非常普遍的一种。使用彩灯即可起装饰宣传作用，又可以现场气氛，城市也因为众多的彩灯而变得灿烂辉煌。VHDL语言作为可编程逻辑器件的标准语言描述能力强，覆盖面广，抽象能力强，在实际应用中越来越广泛。在这个阶段，人们开始追求贯彻整个系统设计的自动化，可以从繁重的设计工作中彻底解脱出来，把精力集中在创造性的方案与概念构思上，从而可以提高设计效率，缩短产品的研制周期。整个过程通过EDA工具自动完成，大大减轻了设计人员的工作强度，提高了设计质量，减少了出错的机会。要求设计一个8路彩灯控制器,要求彩灯可以演示以下花型：（1） 从两边向中间亮，再从中间向两边亮；（2） 实现淡入淡出效果（3） 从左至右逐个亮，在从右到左逐个亮；2. 总体设计2.1 各个花样的状态图当选择花样一时状态图如下：S0=”ZZZZZZZZ” S1=10000001S2=01000010S3=00100100 S4=00011000 S5=00100100S6=01000010S0S1CLRS2S6S3S5S4当选择花样二时状态图如下： S0=”ZZZZZZZZ” S1=00000000S2=10000000S3=11000000S4=11100000 S5=11110000S6=11111000S7=”11111100”S8=”11111110” S9=11111111S10=01111111S11=00111111S12=00011111 S13=00001111S14=00000111S15=”00000011”S16=”00000001”S0s1 CLRS16S2 S4S15S5s14s6s13S7s12S8s11S9s10 当选择花样三时状态图如下：S0=”ZZZZZZZZ” S1=10000000S2=01000000S3=00100000S4=00010000 S5=00001000S6=00000100S7=”00000010”S8=”00000001” S9=00000010S10=00000100S11=00001000S12=0001000 S13=00100000S14=01000000S0s1 CLRS2s14 S3s13S4s12s11S5s10s6S7S9S82.2总体框图分频器 CLK状态机LED显示选择器 XUAN 3. 模块设计3.1分频器模块 -由于机器时钟周期太短,不能满足要求 -此模块实现分频,得到需要的时钟LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;USE IEEE.std_logic_unsigned.ALL;ENTITY fenpinqi ISPORT( CLK:IN STD_LOGIC; -原机器时钟 CLR:IN STD_LOGIC; CLK1:OUT STD_LOGIC); -分频后的时钟END fenpinqi;ARCHITECTURE ART OF fenpinqi ISSIGNAL CK:STD_LOGIC; BEGIN PROCESS(CLK,CLR)IS VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN IF CLR=1 THEN CK=0; TEMP:=000; ELSIF(CLKEVENT AND CLK=1)THEN IF TEMP=111 THEN TEMP:=000; CK=NOT CK; ELSE TEMP:=TEMP+1; END IF; END IF; END PROCESS; CLK1=CK;END ART;3.2花样一模块 -用分频器分频后的时钟来显示花样实现 -从两边向中间亮，再从中间向两边亮；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY hy1 IS PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY hy1;ARCHITECTURE ART OF hy1 IS TYPE STATE IS(S0,S1,S2,S3,S4,S5,S6); -设计状态机,实现花样转换 SIGNAL CURRENT_STATE:STATE; SIGNAL LIGHT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS(CLR,CLK1,XUAN)IS -定义花样(1为灯亮,0为灯灭) CONSTANT L1:STD_LOGIC_VECTOR(7 DOWNTO 0):=10000001; CONSTANT L2:STD_LOGIC_VECTOR(7 DOWNTO 0):=01000010; CONSTANT L3:STD_LOGIC_VECTOR(7 DOWNTO 0):=00100100; CONSTANT L4:STD_LOGIC_VECTOR(7 DOWNTO 0):=00011000; CONSTANT L5:STD_LOGIC_VECTOR(7 DOWNTO 0):=00100100;CONSTANT L6:STD_LOGIC_VECTOR(7 DOWNTO 0):=01000010; BEGINIF XUAN=01 THENIF CLR=1 THENCURRENT_STATE LIGHT=ZZZZZZZZ; CURRENT_STATE LIGHT=L1; CURRENT_STATE LIGHT=L2; CURRENT_STATE LIGHT=L3; CURRENT_STATE LIGHT=L4; CURRENT_STATE LIGHT=L5; CURRENT_STATE LIGHT=L6; CURRENT_STATE=S1;END CASE;END IF;END IF; END PROCESS; LED1=LIGHT;END ART;3.3花样二模块 -用分频器分频后的时钟来显示花样实现 -实现淡入淡出效果LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY hy2 IS PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY hy2;ARCHITECTURE ART OF hy2 IS -设计状态机,实现花样转换 TYPE STATE IS(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16); SIGNAL CURRENT_STATE:STATE; SIGNAL LIGHT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS(CLR,CLK1,XUAN)IS -定义花样(1为灯亮,0为灯灭) CONSTANT L1:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000000; CONSTANT L2:STD_LOGIC_VECTOR(7 DOWNTO 0):=10000000; CONSTANT L3:STD_LOGIC_VECTOR(7 DOWNTO 0):=11000000; CONSTANT L4:STD_LOGIC_VECTOR(7 DOWNTO 0):=11100000; CONSTANT L5:STD_LOGIC_VECTOR(7 DOWNTO 0):=11110000; CONSTANT L6:STD_LOGIC_VECTOR(7 DOWNTO 0):=11111000; CONSTANT L7:STD_LOGIC_VECTOR(7 DOWNTO 0):=11111100; CONSTANT L8:STD_LOGIC_VECTOR(7 DOWNTO 0):=11111110; CONSTANT L9:STD_LOGIC_VECTOR(7 DOWNTO 0):=11111111; CONSTANT L10:STD_LOGIC_VECTOR(7 DOWNTO 0):=01111111; CONSTANT L11:STD_LOGIC_VECTOR(7 DOWNTO 0):=00111111; CONSTANT L12:STD_LOGIC_VECTOR(7 DOWNTO 0):=00011111; CONSTANT L13:STD_LOGIC_VECTOR(7 DOWNTO 0):=00001111; CONSTANT L14:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000111; CONSTANT L15:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000011; CONSTANT L16:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000001; BEGINIF XUAN=10 THENIF CLR=1 THENCURRENT_STATE LIGHT=ZZZZZZZZ; CURRENT_STATE LIGHT=L1; CURRENT_STATE LIGHT=L2; CURRENT_STATE LIGHT=L3; CURRENT_STATE LIGHT=L4; CURRENT_STATE LIGHT=L5; CURRENT_STATE LIGHT=L6; CURRENT_STATE LIGHT=L7; CURRENT_STATE LIGHT=L8; CURRENT_STATE LIGHT=L9; CURRENT_STATE LIGHT=L10; CURRENT_STATE LIGHT=L11; CURRENT_STATE LIGHT=L12; CURRENT_STATE LIGHT=L13; CURRENT_STATE LIGHT=L14; CURRENT_STATE LIGHT=L15; CURRENT_STATE LIGHT=L16; CURRENT_STATE=S1;END CASE;END IF;END IF; END PROCESS; LED2=LIGHT;END ART;3.4花样三模块 -用分频器分频后的时钟来显示花样实现 -从左至右逐个亮，在从右到左逐个亮LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY hy3 IS PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY hy3;ARCHITECTURE ART OF hy3 IS -设计状态机,实现花样转换 TYPE STATE IS(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14); SIGNAL CURRENT_STATE:STATE; SIGNAL LIGHT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS(CLR,CLK1,XUAN)IS -定义花样(1为灯亮,0为灯灭) CONSTANT L1:STD_LOGIC_VECTOR(7 DOWNTO 0):=10000000; CONSTANT L2:STD_LOGIC_VECTOR(7 DOWNTO 0):=01000000; CONSTANT L3:STD_LOGIC_VECTOR(7 DOWNTO 0):=00100000; CONSTANT L4:STD_LOGIC_VECTOR(7 DOWNTO 0):=00010000; CONSTANT L5:STD_LOGIC_VECTOR(7 DOWNTO 0):=00001000; CONSTANT L6:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000100; CONSTANT L7:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000010; CONSTANT L8:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000001; CONSTANT L9:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000010; CONSTANT L10:STD_LOGIC_VECTOR(7 DOWNTO 0):=00000100; CONSTANT L11:STD_LOGIC_VECTOR(7 DOWNTO 0):=00001000; CONSTANT L12:STD_LOGIC_VECTOR(7 DOWNTO 0):=00010000; CONSTANT L13:STD_LOGIC_VECTOR(7 DOWNTO 0):=00100000; CONSTANT L14:STD_LOGIC_VECTOR(7 DOWNTO 0):=01000000; BEGINIF XUAN=11 THENIF CLR=1 THENCURRENT_STATE LIGHT=ZZZZZZZZ; CURRENT_STATE LIGHT=L1; CURRENT_STATE LIGHT=L2; CURRENT_STATE LIGHT=L3; CURRENT_STATE LIGHT=L4; CURRENT_STATE LIGHT=L5; CURRENT_STATE LIGHT=L6; CURRENT_STATE LIGHT=L7; CURRENT_STATE LIGHT=L8; CURRENT_STATE LIGHT=L9; CURRENT_STATE LIGHT=L10; CURRENT_STATE LIGHT=L11; CURRENT_STATE LIGHT=L12; CURRENT_STATE LIGHT=L13; CURRENT_STATE LIGHT=L14; CURRENT_STATE=S1;END CASE;END IF;END IF; END PROCESS; LED3=LIGHT;END ART;3.5顶层设计 -将以上几个模块整合起来,实现八路彩灯的花样控制LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY caideng IS PORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ENTITY caideng;ARCHITECTURE ART OF caideng IS COMPONENT fenpinqi -对分频器模块进行定义 PORT( CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; CLK1:OUT STD_LOGIC); END COMPONENT fenpinqi; COMPONENT hy1 -对花样一模块进行定义 PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT hy1; COMPONENT hy2 -对花样二模块进行定义 PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT hy2; COMPONENT hy3 -对花样三模块进行定义 PORT(CLK1:IN STD_LOGIC; CLR:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); LED3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END COMPONENT hy3;SIGNAL S:STD_LOGIC; -定义中间变量SIGNAL L1:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL L2:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL L3:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN U1:fenpinqi PORT MAP(CLK,CLR,S); -对分频器模块进行例化U2:hy1 PORT MAP(S,CLR,XUAN,L1); -对花样一模块进行定义U3:hy2 PORT MAP(S,CLR,XUAN,L2); -对花样二模块进行例化U4:hy3 PORT MAP(S,CLR,XUAN,L3); -对花样三模块进行例化LED=L1 WHEN XUAN=01 ELSE -让LED显示选定的花样 L2 WHEN XUAN=10 ELSE L3;END ART;4. 仿真图4.1分频器仿真波形CLK为输入，是机器时钟。上升沿有效CLR为输入，是异步复位端，当为高电平时有效，CLK1保持状态CLK1为输出，是分频后得到的我们需要的时钟，周期是原时钟的十六倍4.2花样一仿真波形CLK1为输入，是分频后得到的时钟CLR为输入，是异步复位端，当为高电平时有效XUAN是输入，进行选择花样.此时选择的是花样一LED1是输出,用来显示花样实现从两边向中间亮，再从中间向两边亮,运行结果正确4.3花样二仿真波形CLK1为输入，是分频后得到的时钟CLR为输入，是异步复位端，当为高电平时有效XUAN是输入，进行选择花样.此时选择的是花样二LED1是输出,用来显示花样实现淡入淡出效果,运行结果正确4.4花样三仿真波形CLK1为输入，是分频后得到的时钟CLR为输入，是异步复位端，当为高电平时有效XUAN是输入，进行选择花样.此时选择的是花样二LED1是输出,用来显示花样从左