北邮 VHDL时序逻辑电路设计部分实验VHDL源代码.doc

（写的有点简陋，见谅哈,各位）VHDL时序设计逻辑电路设计（一）四位二进制减计数器（摘自网上） library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count1 is port (ci:in std_logic; -计数信号 reset: in std_logic; -异步复位 load: in std_logic; -同步置数 clk: in std_logic; d : in std_logic_vector(3 downto 0); -置数值 q : buffer std_logic_vector(3 downto 0); co: out std_logic -计数溢出标志 );end count1;architecture behave of count1 isbegin process(clk,reset) begin if(reset=0) then q=0000; elsif(clkevent and clk=1) then if(load=1) then q=d; elsif(ci=1) then if(q=0) then q=1111; co=1; else q=q-1; co=0; end if; end if; end if; end process;end behave; VHDL时序设计逻辑电路设计（二）（一）带异步复位的4位能自动启动环形计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY HUANXINGJISHU IS PORT(clk,rs:IN STD_LOGIC; countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END HUANXINGJISHU;ARCHITECTURE behave OF HUANXINGJISHU IS SIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(rs,clk) BEGIN IF rs=0 THEN QQQQQQQQQQQQQQQQQQ=0000; END CASE; END IF; END PROCESS;countout=Q;END behave;（二）带异步复位的4位能自启动扭形计数器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY NIUHUAIJISHU IS PORT(clk,rs:IN STD_LOGIC; countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END NIUHUAIJISHU ;ARCHITECTURE behave OF NIUHUAIJISHU IS SIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(rs,clk) BEGIN IF rs=0 THEN QQQQQQQQQQQQQQQQQQ=0000; END CASE; END IF; END PROCESS;countout=Q;END behave;VHDL时序逻辑电路设计（三）（一）带控制端的8位二进制寄存器：先生成一VHDL file文件，编译以下底层的D触发器文件：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DCHUFAQI IS PORT (d,clk:IN STD_LOGIC; q:OUT STD_LOGIC);END DCHUFAQI;ARCHITECTURE one OF DCHUFAQI ISBEGIN PROCESS BEGIN WAIT UNTIL clk=1; q=d; END PROCESS ;END one;再在同一工程下生成一VHDL文件，源代码如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JICUNQI IS PORT(d: IN STD_LOGIC_VECTOR (7 DOWNTO 0); oe,clk: IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END JICUNQI;ARCHITECTURE struc OF JICUNQI IS COMPONENT DCHUFAQI PORT(d,clk:IN STD_LOGIC; q: OUT STD_LOGIC); END COMPONENT; SIGNAL temp:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN PROCESS(clk,oe) BEGIN IF oe=1 THEN q=ZZZZZZZZ; ELSE q=temp; END IF; END PROCESS; u0:DCHUFAQI PORT MAP(d(0),clk,temp(0); u1:DCHUFAQI PORT MAP(d(1),clk,temp(1); u2:DCHUFAQI PORT MAP(d(2),clk,temp(2); u3:DCHUFAQI PORT MAP(d(3),clk,temp(3); u4:DCHUFAQI PORT MAP(d(4),clk,temp(4); u5:DCHUFAQI PORT MAP(d(5),clk,temp(5); u6:DCHUFAQI PORT MAP(d(6),clk,temp(6); u7:DCHUFAQI PORT MAP(d(7),clk,temp(7);END struc;（二）带控制端的8位二进制锁存器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SUOCUNQI IS PORT( d:IN STD_LOGIC_VECTOR(7 DOWNTO 0); oe,clk:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END SUOCUNQI;ARCHITECTURE struc OF SUOCUNQI IS SIGNAL temp:STD_LOGIC_VECTOR(7