数字时钟设计报告 精品.docx

设计题目 数字时钟一、题目分析用Verilog设计一个多功能的数字钟，具体功能为： （1）、计时功能：时、分、秒的计时； （2）、校时功能：对时、分、秒进行手动调整以校准时间； （3）、整点报时功能：每逢整点，由蜂鸣器产生2秒的“滴 滴”的报时音。二、选择方案多功能数字钟电路的设计总体方案，时钟脉冲为CLK和CLK1，CLK=1Hz，对秒进行计数，当秒计数为60时，产生脉冲控制分，当分计数为60时对，产生脉冲控制时，当时计数为23，分为59，秒为59时，下一脉冲来临时则重新计时恢复为00时00分00秒，并且报时，时间为两秒，报时频率由CLK1控制。按键部分：复位键：高低平有效；设定时间键：高电平有效；时间控制键：高电平控制对分的设定，低电平控制对时的设定；键（IO49，IO42，IO48，IO43）四个控制时分的高四位，键（IO47，IO44，IO46，IO45）四个控制时分的低四位。当设定时间时，使定时间键为高电平，当时间控制键为高电平时，使用键（IO49，IO42，IO48，IO43）和（IO47，IO44，IO46，IO45）可以对分进行设定；使定时间键为高电平，当时间控制键为低电平时；使用键（IO49，IO42，IO48，IO43）和（IO47，IO44，IO46，IO45）可以对时进行设定。当时间为整点时，蜂鸣器报时，时间持续2秒。三、细化框图ENMINENSECRESET图1四、应用程序并仿真4.1秒模块图2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SECOND IS -秒实体 PORT(CLK,RESET:IN STD_LOGIC; SEC:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0); ENSEC:OUT STD_LOGIC); -驱动分计时信号END;ARCHITECTURE A OF SECOND IS-秒结构体BEGINPROCESS(CLK,RESET)BEGINIF RESET=1THEN SEC=00000000;ELSIF CLKEVENT AND CLK=1THENIF SEC=01011001THEN SEC=00000000;ENSEC=1001 THEN SEC(7 DOWNTO 4)=sec(7 DOWNTO 4)+1; SEC(3 DOWNTO 0)=0000; ELSE SEC(3 DOWNTO 0)=sec(3 DOWNTO 0)+1;ensec=0;END IF;END IF;END PROCESS;END;图34.2分模块图4LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MINUTE IS-分实体PORT(CLKM,SET,RESET,MINH:IN STD_LOGIC; SET1:IN STD_LOGIC_VECTOR(7 DOWNTO 0); MIN:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0); ENMIN:OUT STD_LOGIC);-驱动时计时信END;ARCHITECTURE A OF MINUTE IS-分结构体BEGINPROCESS(CLKM,RESET,SET,MINH)BEGINIF RESET=1THEN MIN=00000000;ELSIF SET=1AND MINH=1THEN MIN=SET1;ELSIF CLKMEVENT AND CLKM=1THENIF MIN=01011001THEN MIN=00000000;ENMIN=1001 THEN-进位语句 MIN(7 DOWNTO 4)=MIN(7 DOWNTO 4)+1; MIN(3 DOWNTO 0)=0000; ELSE MIN(3 DOWNTO 0)=MIN(3 DOWNTO 0)+1;ENMIN=0;END IF;END IF;END PROCESS;END;图54.3时模块图6LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY HOUR1 IS -时实体PORT(CLKH,SET,RESET,MINH:IN STD_LOGIC; SET1:IN STD_LOGIC_VECTOR(7 DOWNTO 0); HOUR:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);END;ARCHITECTURE A OF HOUR1 IS-时结构体体BEGINPROCESS(CLKH,RESET,SET,MINH)BEGINIF RESET=1THEN HOUR=00000000;ELSIF SET=1AND MINH=0THEN HOUR=SET1;ELSIF CLKHEVENT AND CLKH=1THENIF HOUR=00100011THEN HOUR=1001 THEN-进位 HOUR(7 DOWNTO 4)=HOUR(7 DOWNTO 4)+1; HOUR(3 DOWNTO 0)=0000; ELSE HOUR(3 DOWNTO 0)=HOUR(3 DOWNTO 0)+1;END IF;END IF;END PROCESS;END;图74.5报时模块图8LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ALARM1 IS-报时实体PORT(RESET,CLK1:IN STD_LOGIC; SEC,MIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0); ALARM:OUT STD_LOGIC);END;ARCHITECTURE A OF ALARM1 IS-报时结构体BEGIN PROCESS(CLK1,SEC,MIN,RESET) BEGINIF MIN=00000000 AND RESET=0 AND (SEC=00000000 OR SEC=00000001) THEN ALARM=CLK1;-报时语句，持续两秒ELSE ALARMRESET,SEC=SEC,CLK=CLK, ENSEC=ENM);u2:MINUTE PORT MAP(RESET=RESET,SET=SETT,SET1=SET11,MINH=MINHH,MIN=MIN,CLKM=ENM,ENMIN=ENH);u3:HOUR1 PORT MAP(RESET=RESET,SET=SETT,SET1=SET11,MINH=MINHH,HOUR=HOUR, CLKH=ENH);u4:ALARM1 PORT MAP(RESET=RESET,MIN=MIN,SEC=SEC,CLK1=CLK1,ALARM=ALARM);END;秒模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SECOND IS -秒实体 PORT(CLK,RESET:IN STD_LOGIC; SEC:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0); ENSEC:OUT STD_LOGIC); -驱动分计时信号END;ARCHITECTURE A OF SECOND IS-秒结构体BEGINPROCESS(CLK,RESET)BEGINIF RESET=1THEN SEC=00000000;ELSIF CLKEVENT AND CLK=1THENIF SEC=01011001THEN SEC=00000000;ENSEC=1001 THEN SEC(7 DOWNTO 4)=sec(7 DOWNTO 4)+1; SEC(3 DOWNTO 0)=0000; ELSE SEC(3 DOWNTO 0)=sec(3 DOWNTO 0)+1;ensec=0;END IF;END IF;END PROCESS;END;分模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MINUTE IS-分实体PORT(CLKM,SET,RESET,MINH:IN STD_LOGIC; SET1:IN STD_LOGIC_VECTOR(7 DOWNTO 0); MIN:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0); ENMIN:OUT STD_LOGIC);-驱动时计时信END;ARCHITECTURE A OF MINUTE IS-分结构体BEGINPROCESS(CLKM,RESET,SET,MINH)BEGINIF RESET=1THEN MIN=00000000;ELSIF SET=1AND MINH=1THEN MIN=SET1;ELSIF CLKMEVENT AND CLKM=1THENIF MIN=01011001THEN MIN=00000000;ENMIN=1001 THEN-进位语句 MIN(7 DOWNTO 4)=MIN(7 DOWNTO 4)+1; MIN(3 DOWNTO 0)=0000; ELSE MIN(3 DOWNTO 0)=MIN(3 DOWNTO 0)+1;ENMIN=0;END IF;END IF;END PROCESS;END;时模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY HOUR1 IS -时实体PORT(CLKH,SET,RESET,MINH:IN STD_LOGIC; SET1:IN STD_LOGIC_VECTOR(7 DOWNTO 0); HOUR:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);END;ARCHITECTURE A OF HOUR1 IS-时结构体体BEGINPROCESS(CLKH,RESET,SET,MINH)BEGINIF RESET=1THEN HOUR=00000000;ELSIF SET=1AND MINH=0THEN HOUR=SET1;ELSIF CLKHEVENT AND CLKH=1THENIF HOUR=00100011THEN HOUR=1001 THEN-进位 HOUR(7 DOWNTO 4)=HOUR(7 DOWNTO 4)+1; HOUR(3 DOWNTO 0)=0000; ELSE HOUR(3 DOWNTO 0)=HOUR(3 DOWNTO 0)+1;END IF;END IF;END PROCESS;END;报警模块LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ALARM1 IS-报时实体PORT(RESET,CLK1:IN STD_LOGIC; SEC,M