17IntroducethePCBLayout.ppt

IntroducethePCBLayout PresentedbyNinaMiaoNDC2004 02Ver 2 0 PCBLayoutSystem 1 Padstack2 ComponentSymbols3 BoardDesign4 ImportingLogicInformationintoAllegro5 SettingDesignConstraints6 ComponentPlacement7 Routing8 Via9 TestPoint 1 Padstack 1 1Createaflashsymbol1 2Createpadstacks1 3AnatomyofaPadstack1 4PadstackDetails 1 Padstack Cont 1 1Createaflashsymbolusedforthermalreliefs Athermalreliefisaspecialpatternusedwhereconnectionsaremadetoanembeddedplanethatallowsheattoconcentratenearapinorviaduringthesolderingprocess 1 Padstack Cont 1 2Createpadstacksforanumberoftypicalpinsanddevicetypes a Createapadstackforathrough holepin b Createapadstackforpin1ofathrough holepin c Createapadstackforasurface mounteddevice 1 Padstack Cont 1 3AnatomyofaPadstack 1 Padstack Cont 1 4PadstackDetails 2 Packagesymbol 2 1Symboltypes 2 Packagesymbol Cont Footprintsymbolsmodelthecomponentsthatareplacedontheprintedcircuitboard stylesoffootprintsincludingDIP SOIC PLCC QFPandsoon Whencreatethefootprint wewilldefineinformationsuchasdesignunits numberofpins pinspacing padstackstouse andsoforth 2 Packagesymbol Cont Packageoutline 3 BoardDesign 3 1BoardOutline 3 BoardDesign Cont 3 BoardDesign Cont 3 2Boardiscomposedof 3 BoardDesign Cont 3 3BoardStack Up 3 BoardDesign Cont 4 3milsPrepreg 48milsCore FR4 4 5milsPrepreg 1 FR4isaspecialmaterialofCore 2 Boardimpedance 60 10 3 BoardDesign Cont 3 4Powerdivide 4 ImportingLogicInformationintoAllegro 4 1LayoutProcess4 2Bringtheschematicdata4 3ImportlogicinformationConceptLogicImportCaptureLogicimportThird PartyLogicImport 4 ImportingLogicInformationintoAllegro Cont 4 1LayoutProcess 4 ImportingLogicInformationintoAllegro Cont 4 2BringschematicdatafromtheConcepttool Capturetool orathird partyfront endtool 4 3SetupandimportlogicinformationintoAllegrofromoneofthethesethreeschematicenvironments Concept HDL Capture Third party 4 ImportingLogicInformationintoAllegro Cont ConceptLogicImport 4 ImportingLogicInformationintoAllegro Cont CaptureLogicimport 4 ImportingLogicInformationintoAllegro Cont Third PartyLogicImport 4 ImportingLogicInformationintoAllegro Cont 5 SettingDesignConstraints 5 SettingDesignConstraints Cont 5 1Therearefourtypesofdesignrules SpacingRuleSet Clearancesbetweenlines pads vias andcopperareas shapes PhysicalRuleSet LinewidthandlayerrestrictionsDesignConstraints Packagechecks soldermaskchecksandnegativeplaneislandchecks 5 SettingDesignConstraints Cont ElectricalConstraintSets Performancecharacteristics crosstalkandpropagationdelay 5 SettingDesignConstraints Cont 5 2Therearetwolevelsofdetailfordesignrules Standardrules Describethemajorityofnetsinadesign Theseglobalrulesareappliedtoallnets allnetsarecreatedequal Extendedrules Areperformancerelated andareassignedonanet by netbasis Timingandspeedconsiderations netlengthandpropagationdelay Noiseanddistortionconcerns crosstalk reflection impedence 6 ComponentPlacement 6 1Theprerequisitesformanualplacementare Thepackagesymbolsandpadstacksrequiredforpartsinthenetlistmustexist YoumustloadaschematicdatabaseintoanAllegrodesignfile brd Youcancreatea blockdiagram ofthelogicalfunctionsthatneedtobearrangedontheboardbyusingRooms 6 ComponentPlacement Cont 6 2Componentplacementstrategy Createroomsforfloorplanning Assignreferencedesignatorsto preplaced devices PlaceI Obounddevices Placecriticallogicfunctions Evaluateandreviseplacement Placebulkdecouplingandbypasscaps Usereportstoaidplacementprocess 6 ComponentPlacement Cont 6 3Setdrawingparameters Placethemechanicalsymbol Addformatsymbols Addpackagesymbols Setcolorandvisibility Definethecrosssection layerstackup 7 Routing 7 1InteractiveroutingmodesDefinenetpropertiesbeforeaddingetch Commonnetpropertiesusedwithinteractiverouteare MIN LINE WIDTHMIN NECK WIDTHNO RATFIXED Addingsignalconnections Deletingsignalconnections Insertingvias 7 2AutomaticRoutingmodes 8 1TypeofVia throughvia blindvia buriedvia 9 TestPoint 9 1Bareboarda Electricalcontinuitycheck opensandshorts b PerformedafterfabricationAfterthephysicalboardhasbeenmanufactured itistestedforcontinuitybythefabricationfacility knownasbareboardtest Thistestcheckstheconnectionsbetweenallcomponentpins andensuresthatno shorts or opens exist 9 TestPoint Cont 9 2In circuita Logicalperformancecheckb PerformedafterassemblyAftertheboardhasbeenassembled itgoesthroughfurthertestingknownasin circuittesting In circuittestingverifiesthattheboardandcom