微波炉控制器源程序.doc

KZQ源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY KZQ ISPORT(RESET:IN STD_LOGIC;SET_T:IN STD_LOGIC;START:IN STD_LOGIC;TEST:IN STD_LOGIC;CLK:IN STD_LOGIC;DONE:IN STD_LOGIC;COOK:OUT STD_LOGIC;LD_TEST:OUT STD_LOGIC;LD_CLK:OUT STD_LOGIC;LD_DONE:OUT STD_LOGIC);END KZQ;ARCHITECTURE one OF KZQ ISTYPE STATES IS(IDLE,LAMP_TEST,SET_CLOCK,TIMER,DONE_MSG);SIGNAL NXT,CUR:STATES;BEGINPROCESS(CLK,RESET)BEGINIF RESET=1THENCUR=IDLE;ELSIF CLKEVENT AND CLK=1THENCUR=NXT;END IF;END PROCESS;PROCESS(CLK,CUR,SET_T,START,TEST,DONE)ISBEGINNXT=IDLE;LD_TEST=0;LD_DONE=0;LD_CLK=0;COOKLD_CLK=1;COOKLD_CLK=1;COOKLD_DONE=1;COOKIF TEST=1THENNXT=LAMP_TEST;LD_TEST=1;ELSIF SET_T=1THENNXT=SET_CLOCK;LD_CLK=1;ELSIF START=1AND DONE=0THENNXT=TIMER;COOKIF DONE=1THENNXT=DONE_MSG;LD_DONE=1;ELSENXT=TIMER;COOK=1;END IF;END CASE;END PROCESS;END one;ZZQ的源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY ZZQ ISPORT(DATAIN:IN STD_LOGIC_VECTOR(15 DOWNTO 0);LD_TEST:IN STD_LOGIC;LD_CLK:IN STD_LOGIC;LD_DONE:IN STD_LOGIC;DATAOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);LOAD:OUT STD_LOGIC); END ZZQ;ARCHITECTURE one OF ZZQ ISBEGINPROCESS(DATAIN,LD_TEST,LD_CLK,LD_DONE)CONSTANT ALLS:STD_LOGIC_VECTOR(15 DOWNTO 0):=1000100010001000;CONSTANT DONE:STD_LOGIC_VECTOR(15 DOWNTO 0):=1010101111001101;VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINLOADDATAOUTDATAOUTDATAOUTNULL;END CASE;END PROCESS;END one;JSQ的源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JSQ ISPORT(COOK:IN STD_LOGIC;LOAD:IN STD_LOGIC;CLK:IN STD_LOGIC;DATA:IN STD_LOGIC_VECTOR(15 DOWNTO 0);SEC0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);SEC1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);MIN0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);MIN1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);DONE:OUT STD_LOGIC);END JSQ;ARCHITECTURE one OF JSQ ISCOMPONENT CNT10 ISPORT(CLK:IN STD_LOGIC;LOAD:IN STD_LOGIC;EN:IN STD_LOGIC;DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CARRY_OUT:OUT STD_LOGIC);END COMPONENT CNT10;COMPONENT CNT6 ISPORT(CLK:IN STD_LOGIC;LOAD:IN STD_LOGIC;EN:IN STD_LOGIC;DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CARRY_OUT:OUT STD_LOGIC);END COMPONENT CNT6;SIGNAL CLK0:STD_LOGIC;SIGNAL S0:STD_LOGIC;SIGNAL S1:STD_LOGIC;SIGNAL S2:STD_LOGIC;SIGNAL S3:STD_LOGIC;BEGINU1:CNT10 PORT MAP(CLK,LOAD,COOK,DATA(3 DOWNTO 0),SEC0,S0);U2:CNT6 PORT MAP(S0,LOAD,COOK,DATA(7 DOWNTO 4),SEC1,S1);U3:CNT10 PORT MAP(S1,LOAD,COOK,DATA(11 DOWNTO 8),MIN0,S2);U4:CNT6 PORT MAP(S2,LOAD,COOK,DATA(15 DOWNTO 12),MIN1,S3);DONE=S0 AND S1 AND S2 AND S3;END one;CNT10的源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT(CLK:IN STD_LOGIC;LOAD:IN STD_LOGIC;EN:IN STD_LOGIC;DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CARRY_OUT:OUT STD_LOGIC);END CNT10;ARCHITECTURE one OF CNT10 ISSIGNAL TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,LOAD,EN)BEGINIF LOAD=1THENTMP=DATAIN;ELSIF CLKEVENT AND CLK=1THENIF EN=1THENIF TMP=0000THENTMP=1001;ELSETMP=TMP-1;END IF;END IF;END IF;END PROCESS;PROCESS(CLK,TMP)BEGINIF CLKEVENT AND CLK=1THENIF TMP=0000THENCARRY_OUT=1;ELSECARRY_OUT=0;END IF;END IF;END PROCESS;Q=TMP;END one;CNT6的源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT6 ISPORT(CLK:IN STD_LOGIC;LOAD:IN STD_LOGIC;EN:IN STD_LOGIC;DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CARRY_OUT:OUT STD_LOGIC);END CNT6;ARCHITECTURE one OF CNT6 ISSIGNAL TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,LOAD,EN)BEGINIF LOAD=1THENTMP=DATAIN;ELSIF CLKEVENT AND CLK=1THENIF EN=1THENIF TMP=0000THENTMP=0101;ELSETMP=TMP-1;END IF;END IF;END IF;END PROCESS;PROCESS(CLK,TMP)BEGINIF CLKEVENT AND CLK=1THENIF TMP=0000THENCARRY_OUT=1;ELSECARRY_OUT=0;END IF;END IF;END PROCESS;QDOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7=0000000; END CASE; END PROCESS;END ONE;TOP源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TOP ISPORT(DATA:IN STD_LOGIC_VECTOR(15 DOWNTO 0);RESET:IN STD_LOGIC;SET_T:IN STD_LOGIC;START:IN STD_LOGIC;TEST:IN STD_LOGIC;CLK:IN STD_LOGIC;COOK:OUT STD_LOGIC;DOUT0:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);DOUT1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);DOUT2:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);DOUT3:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END TOP;ARCHITECTURE one OF TOP ISCOMPONENT KZQ ISPORT(RESET:IN STD_LOGIC;SET_T:IN STD_LOGIC;START:IN STD_LOGIC;TEST:IN STD_LOGIC;CLK:IN STD_LOGIC;DONE:IN STD_LOGIC;COOK:OUT STD_LOGIC;LD_TEST:OUT STD_LOGIC;LD_CLK:OUT STD_LOGIC;LD_DONE:OUT STD_LOGIC);END COMPONENT KZQ;COMPONENT ZZQ ISPORT(DATAIN:IN STD_LOGIC_VECTOR(15 DOWNTO 0);LD_TEST:IN STD_LOGIC;LD_CLK:IN STD_LOGIC;LD_DONE:IN STD_LOGIC;DATAOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);LOAD:OUT STD_LOGIC);END COMPONENT ZZQ;COMPONENT JSQ ISPORT(COOK:IN STD_LOGIC;LOAD:IN STD_LOGIC;CLK:IN STD_LOGIC;DATA:IN STD_LOGIC_VECTOR(15 DOWNTO 0);SEC0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);SEC1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);MIN0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);MIN1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);DONE:OUT STD_LOGIC);END COMPONENT JSQ;COMPONENT YMQ ISPORT(AIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT7:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END COMPONENT;SIGNAL COOK_TMP:STD_LOGIC;SIGNAL TEST_TMP:STD_LOGIC;SIGNAL CLK_TMP:STD_LOGIC;SIGNAL DONE_TMP:STD_LOGIC;SIGNAL LOAD_TMP:STD_LOGIC;SIGNAL DONE:STD_LOGIC;SIGNAL DATA_TMP:STD_LOGIC_VECTOR(15 DOWNTO 0);SIGNAL SEC0_TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL SEC1_TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL MIN0_TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL MIN1_TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINCOOK=COOK_TMP;U1:KZQ PORT MAP(RESET,SET_T,START,TEST,CLK,DONE,COOK_TMP,TEST_TMP,CLK_TMP,DONE_T