串入并出转换器-verilog.doc

设计一个串入并出转换器。输入是8bit数据，输出是32bit数据。给出AMSD图和HDL设计描述。提交纸质文档。一、ASMD图2、 RTL代码/*程序名称：串入并出转换器简要说明：串行输入8bit数据，并行输出32bit数据。编 写：武书肖最后更新：2015年3月28日 星期六*/module ser_to_par(clk,rst_n,en,data_in,data_out,en_out);input clk,rst_n,en;input 7:0 data_in; /8位串行输入output 31:0 data_out; /32位并行输出output en_out; /输出有效标志位reg 7:0 p0,p1,p2,p3; /4个8位寄存器reg 31:0 data_reg; /32位输出寄存器reg 4:0 state,next_state; /FSM状态reg en_out;parameter s_idle=5b00001, /状态独热编码 s_in_1=5b00010, s_in_2=5b00100, s_in_3=5b01000, s_full=5b10000;assign data_out=en_out?data_reg:32dz;always (posedge clk) /同步时序描述状态转移begin if(rst_n=0) state=s_idle;else state=next_state;endalways (state or en ) /组合逻辑描述状态转移条件判断begin next_state=state;case(state)s_idle: if(en=1) next_state=s_in_1; else next_state=s_idle; s_in_1: next_state=s_in_2;s_in_2: next_state=s_in_3;s_in_3: next_state=s_full;s_full: if(en=1) next_state=s_in_1; else next_state=s_idle;endcase endalways (posedge clk) /同步时序描述次态寄存器的输出begin if(rst_n=0) en_out=0; else case(next_state)s_idle: en_out=0; s_in_1,s_in_2,s_in_3: begin en_out=0;p3=data_in;p2=p3;p1=p2;p0=p1;ends_full: begin data_reg=p3,p2,p1,p0;en_out=1;if(en=1) p3=data_in;endendcaseendendmodule /*不使用状态机的RTL代码*/module ser_to_par(clk,rst_n,en,data_in,data_out,en_out);input clk,rst_n,en;input 7:0 data_in; /8位串行输入output 31:0 data_out; /32位并行输出output en_out; /输出有效标志位reg 7:0 p0,p1,p2,p3; /4个8位寄存器reg 31:0 data_reg; /32位输出寄存器reg en_out;integer in_counter; /输入数据计数assign data_out=en_out?data_reg:32dz;always (posedge clk) begin if(!rst_n)begin in_counter=0; en_out=0;endelse if(en)begin in_counter=in_counter+1;en_out=0;p3=data_in;p2=p3;p1=p2;p0=p1;data_reg=p3,p2,p1,p0;if(in_counter=3)beginen_out=1;in_counter=0;endendendendmodule 三、 Test Benchtimescale 1 ns/ 1 psmodule seri_to_para_vlg_tst();reg clk;reg 7:0 data_in;reg en;reg rst_n; wire 31:0 data_out;wire en_out; seri_to_para i1 (/ port map - connection between master ports and signals/registers .clk(clk),.data_in(data_in),.data_out(data_out),.en(en),.en_out(en_out),.rst_n(rst_n);initial begin clk=0;rst_n=1;en=0;#10 rst_n=0;#100 rst_n=1;#100 en=1;#10000 $stop; end always #50 clk=clk;always (negedge cl