FPGA底层代码,正弦波,方波,三角波,锯齿波.doc

1 频率控制模块 代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FREQUENCY IS PORT ( CLK : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);-设置A的初值 FOUT : OUT STD_LOGIC ); END; ARCHITECTURE one OF FREQUENCY IS SIGNAL FULL : STD_LOGIC; BEGIN P_REG: PROCESS(CLK) VARIABLE CNT1 : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN IF CLKEVENT AND CLK = 1 THEN IF CNT1 = 11111 THEN CNT1 := A; -当CNT1计数计满时，输入数据D被同步预置给计数器CNT1 FULL = 1; -同时使溢出标志信号FULL输出为高电平 ELSE CNT1 := CNT1 + 1; -否则继续作加1计数 FULL = 0; -且输出溢出标志信号FULL为低电平 END IF; END IF; END PROCESS P_REG P_DIV: PROCESS(FULL) VARIABLE CNT2 : STD_LOGIC; BEGIN IF FULLEVENT AND FULL = 1 THEN CNT2 := NOT CNT2; -如果溢出标志信号FULL为高电平，D触发器输出取反 IF CNT2 = 1 THEN FOUT = 1; ELSE FOUT NULL;WHENOTHERS=a=d(0);-dlt b=d(1);-sqr c=d(2);-sin ENDCASE; ENDPROCESS;END;三角波信号产生模块代码libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitydeltaisport(clk:instd_logicclr:instd_logic; q:outstd_logic_vector(7downto0)enddelta;architectureoneofdeltaisbeginprocess(clk,clr)variablenum:std_logic_vector(7downto0);variableff:std_logic;beginifclr=0thennum:=00000000;elseifclkeventandclk=1then-时钟信号有上升沿时有效ifff=0thenifnum=11111000thenff:=1;elsenum:=num+8;endif;-以上，ff=0时，上升，直至num加到11111000时，使ff=1elseifnum=00000111thennum:=00000000;ff:=0;elsenum:=num-8;-以上，ff=1时，下降，直至num减到00000111时，使ff=0endif;endif;endif;endif;q=num;-每一次脉冲，将num的值给q以输出endprocessend;四方波信号产生模块代码libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityaquareisport(clk:instd_logicclr:instd_logic; q:outstd_logic_vector(7downto0)endaquare;architectureoneofaquareissignalff:bit;beginp1:process(clk,clr)variablenum:std_logic_vector(5downto0);beginifclr=0thenff=0;elseifclkeventandclk=1then-当时钟脉冲有一个上升沿ifnum31thennum:=num+1;elsenum:=000000;ff=notff;-num每次加1，加32次ff取反1次endif;endif;endif;endprocessp1;p2:process(clk,ff)beginifclkeventandclk=1thenifff=1thenq=11111111;-ff=1时输出高电平elseq=00000000;-ff=0时输出低电平endif;endif;endprocessp2;end;5 正弦波信号产生模块 代码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sin is port ( clk : in std_logic -正弦信号的相位 clr : in std_logic; d : out std_logic_vector(7 downto 0) ) -正弦函数值 end architecture one of sin is-结构体开始 Begin process( clk,clr)variable num : std_logic_vector(5 downto 0); Begin if clr = 0 then