EDA程序终极汇总(修订后).doc

2009年EDA考试程序汇总（终极版）信息工程学院2009年EDA考试程序汇总（终极版）制作人：柳阳2009年6月23日说明1. 所有程序均来自上课及实验，无压题之意；2. 所有程序均通过编译，波形仿真请自己完成；3. 文字部分由于时间较紧，可能会有错误，望见谅；4. 特别感谢王敏聪同学在程序方面给予的指导和帮助。1.组合逻辑电路：(1)半加器与全加器（原理图以及VHDL语言）A半加器输入：2个二进制1位输出：和输出S，进位Co真值表：ABSCo0000011010101101程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY HALFADD ISPORT(A,B: IN STD_LOGIC;S,Co: OUT STD_LOGIC);END HALFADD;ARCHITECTURE RTL OF HALFADD ISBEGINS = A XOR B;Co A,B=B,S=T1,CO=T2);U2: HALFADD PORT MAP( A=CI,B=T1,S=S,CO=T3);Co = T2 OR T3;END RTL;原理图：A分层开发B单层开发（课本P114）(2)全减器（原理图以及VHDL语言）输入：2个二进制1位，一个借位输入Ci输出：差输出S，借位Co真值表：ABCiSCo0000000111010110110110010101001100011111程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY FULL_SUBB ISPORT( A,B,CI:IN STD_LOGIC; S,CO:OUT STD_LOGIC);END FULL_SUBB;ARCHITECTURE RTL OF FULL_SUBB ISSIGNAL NA:STD_LOGIC;BEGINNA=NOT A;S=A XOR B XOR CI;CO=(NA AND CI) OR (B AND CI) OR (NA AND B);END RTL;原理图：(3) 译码器（以下程序均非译码器程序，具体译码器程序可参照数字钟4-7译码器程序）A2-4译码器输入端口：2个二进制输入端a、b输入端口：1个使能控制信号en输出端口：4个译码输出端y0 y3真值表：输入输出ENABY3Y2Y1Y00ZZZZ1000001101001011001001111000程序：（程序为四选一选择器，真值表及原理图为2-4译码器）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX4 ISPORT( Y0,Y1,Y2,Y3,A,B,EN:IN STD_LOGIC; Q:OUT STD_LOGIC);END MUX4;ARCHITECTURE RTL OF MUX4 ISSIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINSEL=A & B;PROCESS(SEL)BEGINIF EN=0 THENQ=Z;ELSEIF SEL=00 THEN Q=Y0;ELSIF SEL=01 THEN Q=Y1;ELSIF SEL=10 THEN Q=Y2;ELSIF SEL=11 THEN Q=Y3; END IF;END IF; END PROCESS;END RTL;原理图：B3-8译码器（程序为八选一选择器，真值表及原理图为3-8译码器）输入端口：3个二进制输入端T0,T1,T2输入端口：1个使能控制信号EN输出端口：4个译码输出端A0 A7真值表：输入输出ENT2T1T0A7A6A5A4A3A2A1A00ZZZZZZZZ100000000001100100000010101000000100101100001000110000010000110100100000111001000000111110000000程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX8 ISPORT(A0,A1,A2,A3,A4,A5,A6,A7:IN STD_LOGIC_VECTOR(7 DOWNTO 0);T0,T1,T2,EN:IN STD_LOGIC;Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END MUX8;ARCHITECTURE RTL OF MUX8 ISSIGNAL SEL:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINSEL=T2&T1&T0;PROCESS(SEL)BEGINIF EN=0 THENY = ZZZZZZZZ;ELSEIF SEL=000 THEN Y=A0;ELSIF SEL=001 THEN Y=A1;ELSIF SEL=010 THEN Y=A2;ELSIF SEL=011 THEN Y=A3;ELSIF SEL=100 THEN Y=A4;ELSIF SEL=101 THEN Y=A5;ELSIF SEL=110 THEN Y=A6;ELSIF SEL=111 THEN Y=A7;END IF;END IF;END PROCESS;END RTL;(4)编码器A优先编码器（8-3）真值表：输入输出SD0D1D2D3D4D5D6D7Q2Q1Q0GsE011111101111111111110000000100100101001101001001110110100111110001001111110101001111111100100111111111101程序：（真值表为优先编码器真值表，程序为普通编码器程序）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY i_encoder ISPORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);S: IN STD_LOGIC;Gs,E0: OUT STD_LOGIC;Q: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);END i_encoder ;ARCHITECTURE RTL OF i_encoder ISBEGINPROCESS(S,D)BEGINIF (S=1) THENq = 111;Gs = 1;E0= 1;ELSIF (S=0) THENIF ( d = 11111111) THENq = 111;Gs = 1;E0 = 0;ELSIF ( d(7) = 0) THENq = 000;Gs = 0;E0 = 1;ELSIF ( d(6) = 0) THENq = 001;Gs = 0;E0 = 1;ELSIF ( d(5) = 0) THENq = 010;Gs = 0;E0 = 1;ELSIF ( d(4) = 0) THENq = 011;Gs = 0;E0 = 1;ELSIF ( d(3) = 0) THENq = 100;Gs = 0;E0 = 1;ELSIF ( d(2) = 0) THENq = 101;Gs = 0;E0 = 1;ELSIF ( d(1) = 0) THENq = 110;Gs = 0;e0 = 1;ELSIF ( d(1) = 0) THENq = 111;Gs = 0;e0 = 1;END IF;END IF;END PROCESS;END RTL; B普通编码器（4-2）程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ENCODE42 ISPORT(EN:IN STD_LOGIC;I:IN STD_LOGIC_VECTOR(3 DOWNTO 0);A,B:OUT STD_LOGIC);END ENCODE42;ARCHITECTURE RTL OF ENCODE42 ISBEGINPROCESS(EN,I)BEGINIF(EN=0) THEN A=0;B=0;ELSE IF(I(0)=0) THEN A=0;B=0; ELSIF(I(1)=0) THEN A=0;B=1; ELSIF(I(2)=0) THEN A=1;B=0; ELSIF(I(3)=0) THEN A=1;B Q Q Q Q NULL;END CASE;END PROCESS;END RTL;(6)三态门（原理图以及VHDL语言）数据输入din，控制输入en数据输出dout真值表：数据输入控制输入数据输出X0Z010111程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY TAI3 ISPORT(DIN,EN: IN STD_LOGIC;DOUT: OUT STD_LOGIC);END TAI3;ARCHITECTURE RTL OF TAI3 ISBEGINPROCESS(DIN,EN)BEGINIF EN=1 THENDOUT = DIN;ELSEDOUT = Z;END IF;END PROCESS;END RTL;状态图：(7)单向总线缓冲器输入：A_IN,使能端EN输出：A_OUT程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TRI_GATE8 ISPORT(A_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);EN:IN STD_LOGIC;A_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END TRI_GATE8 ;ARCHITECTURE RTL OF TRI_GATE8 ISBEGINPROCESS(EN,A_IN)BEGINIF EN=0 THENA_OUT = ZZZZZZZZ;ELSEA_OUT = A_IN;END IF;END PROCESS;END RTL;(8)双向总线缓冲器双向端口：A B（inout）使能端EN，方向控制端DR真值表：ENDR功能10A=B11B=A0X高阻程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY BITRIBUS ISPORT(DR,EN:IN STD_LOGIC;A,B:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);END BITRIBUS;ARCHITECTURE RTL OF BITRIBUS ISBEGINPROCESS(EN,DR,A,B)BEGINIF(EN=0) THEN A=ZZZZZZZZ;ELSE IF(DR=0) THEN A=B; ELSE A=ZZZZZZZZ; END IF;END IF;END PROCESS;PROCESS(EN,DR,A,B)BEGINIF(EN=0) THEN B=ZZZZZZZZ;ELSE IF(DR=1) THEN B=A; ELSE B=ZZZZZZZZ; END IF;END IF;END PROCESS;END RTL;原理图：(9)三人表决器真值表：输入输出ABCQ00000010010001111000101111011111原理图：(10)火灾报警系统，烟感、温感、紫外光感，两种以上探测器发出信号，系统产生报警（与(9)类似）2.时序逻辑电路：(1)D触发器真值表：数据输入D时钟输入CLK数据输出Q0不变1不变0011程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DFF ISPORT(CLK,D:IN STD_LOGIC;Q:OUT STD_LOGIC);END DFF;ARCHITECTURE RTL OF DFF ISBEGINPROCESS(CLK)BEGINIF CLKEVENT AND CLK=1 THENQ = D;END IF;END PROCESS;END RTL;(2)非同步复位的D锁存器真值表：数据D时钟CLK复位CLR输出Q000/11不变010110程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DFF ISPORT(CLK,CLR,D:IN STD_LOGIC;Q:OUT STD_LOGIC);END DFF;ARCHITECTURE RTL OF DFF ISBEGINPROCESS(CLK,CLR)BEGINIF CLR=0 THENQ=0;ELSEIF CLKEVENT AND CLK=1 THENQ = D;END IF;END IF;END PROCESS;END RTL;(3)同步复位的D锁存器真值表：数据D时钟CLK复位CLR输出Q000/11不变010110程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DFF ISPORT(CLK,CLR,D:IN STD_LOGIC;Q:OUT STD_LOGIC);END DFF;ARCHITECTURE RTL OF DFF ISBEGINPROCESS(CLK,CLR)BEGINIF CLKEVENT AND CLK=1 THENIF CLR=0 THENQ=0;ELSEQ = D;END IF;END IF;END PROCESS;END RTL;(4)异步复位/同步置位的D触发器真值表：输入输出数据D时钟CLK置位PSET复位CLRQ000110/111不变01101111程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DFF_CLR ISPORT(CLK,CLR,PSET,D:IN STD_LOGIC;Q:OUT STD_LOGIC);END DFF_CLR;ARCHITECTURE RTL OF DFF_CLR ISBEGINPROCESS(CLK,CLR)BEGINIF(CLR=0) THEN Q=0;ELSIF(CLKEVENT AND CLK=1) THENIF(PSET=0) THEN Q=1;ELSE Q=D;END IF;END IF;END PROCESS;END RTL;(5)JK触发器真值表：数据输入DJK时钟输入CLK数据输出Q000010010/10100/110101111110程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DFF ISPORT(CLK,J,K,D:IN STD_LOGIC;Q:OUT STD_LOGIC);END DFF;ARCHITECTURE RTL OF DFF ISBEGINPROCESS(CLK,J,K)BEGINIF CLKEVENT AND CLK=1 THENIF J=0 AND K=0 THENQ = D;ELSIF J=0 AND K=1 THENQ = 0;ELSIF J=1 AND K=0 THENQ = 1;ELSIF J=1 AND K=1 THENQ = NOT D;END IF;END IF;END PROCESS;END RTL;(6)串行输入、串行输出寄存器输入端：串行数据，时钟输出端：数据8位串行移位寄存器：在时钟信号的作用下，前级的数据向后级移动程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CRCC ISPORT(CLK,D:IN STD_LOGIC;Q:OUT STD_LOGIC );END CRCC;ARCHITECTURE RTL OF CRCC ISSIGNAL TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(CLK)BEGINIF CLKEVENT AND CLK=1 THENTEMP(7)=D;TEMP(6 DOWNTO 0)=TEMP(7 DOWNTO 1);Q=TEMP(0);END IF;END PROCESS;END RTL; (7)双向移位寄存器真值表：输入输出CLRDIRLOADCLKQ7Q6Q5Q4Q3Q2Q1Q000000000010D7D6D5D4D3D2D1D0101左移一位SL111SH右移一位程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ly1 ISPORT(CLR,CLK,LOAD,DIR:IN STD_LOGIC;SR,SL:IN STD_LOGIC;D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END ly1;ARCHITECTURE RTL OF ly1 ISSIGNAL TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(CLK,CLR)BEGINIF CLR=0 THENTEMP=00000000;ELSIF CLKEVENT AND CLK=1 THENIF LOAD=0 THENTEMP=D;ELSEIF DIR=0 THEN -LEFT SHIFTFOR I IN 0 TO 6 LOOPTEMP(I+1)=TEMP(I);END LOOP;TEMP(0)=SL;ELSE -RIGHT SHIFTFOR I IN 0 TO 6 LOOPTEMP(I)=TEMP(I+1);END LOOP;TEMP(7)=SR;END IF;END IF;END IF;END PROCESS;Q=TEMP;END RTL;(8)循环移位寄存器真值表：输入输出S2S1S0LOADCLKQ7 Q6 Q5 Q4 Q3 Q2 Q1 Q00D7 D6 D5 D4 D3 D2 D1 D00001不循环，保持原值0011循环左移1位0101循环左移2位0111循环左移3位1001循环左移4位1011循环左移5位1101循环左移6位1111循环左移7位程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ly2 ISPORT(CLK,LOAD:IN STD_LOGIC;SNUM:IN STD_LOGIC_VECTOR(2 DOWNTO 0);DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ly2;ARCHITECTURE RTL OF ly2 ISSIGNAL TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(CLK,SNUM)BEGINIF(LOAD=0) THENTEMPDOUT DOUT(7 DOWNTO 1) = TEMP(6 DOWNTO 0);DOUT(0)DOUT(7 DOWNTO 2) = TEMP(5 DOWNTO 0);DOUT(1 DOWNTO 0)DOUT(7 DOWNTO 3) = TEMP(4 DOWNTO 0);DOUT(2 DOWNTO 0)DOUT(7 DOWNTO 4) = TEMP(3 DOWNTO 0);DOUT(3 DOWNTO 0)DOUT(7 DOWNTO 5) = TEMP(2 DOWNTO 0);DOUT(4 DOWNTO 0)DOUT(7 DOWNTO 6) = TEMP(1 DOWNTO 0);DOUT(5 DOWNTO 0)DOUT(7) = TEMP( 0);DOUT(6 DOWNTO 0) DOUT=TEMP;END CASE;END IF;END PROCESS;END RTL;(9)带允许端的十二进制计数器真值表：输入输出CLRENCLKQdQcQbQa1000000不变01计数值加1程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNT12 ISPORT(CLR,CLK,EN:IN STD_LOGIC;QD,QC,QB,QA:OUT STD_LOGIC);END COUNT12 ;ARCHITECTURE RTL OF COUNT12 ISSIGNAL CNT: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINQD=CNT(3);QC=CNT(2);QB=CNT(1);QA=CNT(0);PROCESS(CLK)BEGINIF CLR=1 THENCNT=0000;ELSIF CLKEVENT AND CLK=1 THENIF EN=1 THENIF CNT=1011 THENCNT=0000;ELSECNT=CNT+1;END IF;END IF;END IF;END PROCESS;END RTL;(10)6位二进制可逆计数器真值表：输入输出CLRUPDNCLKQfQeQdQcQbQa100000001计数加100计数减1程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ly3 ISPORT(CLR,CLK,UPDN:IN STD_LOGIC;QF,QE,QD,QC,QB,QA:OUT STD_LOGIC);END ly3;ARCHITECTURE RTL OF ly3 ISSIGNAL CNT: STD_LOGIC_VECTOR(5 DOWNTO 0);BEGINQF=CNT(5);QE=CNT(4);QD=CNT(3);QC=CNT(2);QB=CNT(1);QA=CNT(0);PROCESS(CLK)BEGINIF CLR=1 THENCNT=000000;ELSIF CLKEVENT AND CLK=1 THENIF UPDN=1 THENCNT=CNT+1;ELSECNT=CNT-1;END IF;END IF;END PROCESS;END RTL;(11)模十二分频器程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ly4 ISPORT(CLK:IN STD_LOGIC;Y:OUT STD_LOGIC);END ly4;ARCHITECTURE behav OF ly4 ISSIGNAL Q:INTEGER RANGE 0 TO 11;SIGNAL f:STD_LOGIC;BEGINPROCESS(clk) BEGIN IF (clkEVENT)AND(clk=1)THEN IF Q=5 THEN f=1;Q=Q+1; ELSIF Q=11 THEN f=0;Q=0; ELSE f=0;Q=Q+1; END IF; END IF;Y=f;END PROCESS;END behav;3.状态机：(1)序列信号发生器程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ly5 ISPORT(DIN,CLK,CLR:IN STD_LOGIC;Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END ly5;ARCHITECTURE behav OF ly5 ISSIGNAL Q:INTEGER RANGE 0 TO 8;SIGNAL D:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIND=01100101;PROCESS(CLK,CLR) BEGINIF CLR=1 THEN QIF DIN=D(7) THEN Q=1;ELSE QIF DIN=D(6) THEN Q=2;ELSE QIF DIN=D(5) THEN Q=3;ELSE QIF DIN=D(4) THEN Q=4;ELSE QIF DIN=D(3) THEN Q=5;ELSE QIF DIN=D(2) THEN Q=6;ELSE QIF DIN=D(1) THEN Q=7;ELSE QIF DIN=D(0) THEN Q=8;ELSE QQ=0; END CASE; END IF;END PROCESS;PROCESS(Q) BEGINIF Q=8 THEN Y=0001;ELSE Y=0000;END IF;END PROCESS;END behav;(2)交通灯控制（说明见附一）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY traffic IS PORT(CLK:IN STD_LOGIC;L_G,L_R,L_Y:OUTSTD_LOGIC;R_G,R_R,R_Y:OUT STD_LOGIC);END traffic ;ARCHITECTURE RTL OF traffic IS SIGNAL STATE :STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL START,TIMEOUT :STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL LIGHT:STD_LOGIC_VECTOR(5 DOWNTO 0);SIGNAL CNT1,CNT2:INTEGER RANGE 0 TO 7;BEGINL_G = LIGHT(5); L_Y=LIGHT(4); L_R=LIGHT(3);R_G = LIGHT(2); R_Y=LIGHT(1); R_RLIGHT=010010;START=01;IF (TIMEOUT=01) THEN STATE=01;STARTLIGHT=100100;IF (TIMEOUT=10) THEN STATE=10;STARTLIGHT=010010;IF (TIMEOUT=01) THEN STATE=11;STARTLIGHT=001001;IF (TIMEOUT=10) THEN STATE=00;STARTLIGHT=010010;STATE=00;END CASE;END IF;END PROCESS;PROCESS(CLK)BEGINIF (CLKEVENT AND CLK=1) THEN IF (START=01) THEN IF CNT1=3 THEN TIMEOUT=01;CNT1 =0;ELSECNT1=CNT1+1;END IF;ELSIF (START=10) THEN IF CNT2=5 THEN TIMEOUT=10;CNT2 =0;ELSECNT2=CNT2+1;END IF;END IF;END IF;END PROCESS;END RTL;4.综合(1)汽车尾灯输入：1、使用三个独立的按键：L、R、S2、时钟clk输出：使用六个LED，对应L1L2L3R1R2R3真值表：L1L2L3R1R2R3LEFTL1 L2 L3循环亮RIGHTR1 R2 R3 循环亮STOP全亮全