用VHDL描述下列器件的功能.doc

1 用VHDL描述下列器件的功能（1）集成移位寄存器74194（2）集成计数器74161（1）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY S_R74194 ISPORT(clrn, clk, slsi, srsi: IN STD_LOGIC; din:IN STD_LOGIC_VECTOR(3 DOWNTO 0); ss:IN STD_LOGIC_VECTOR(1 DOWNTO 0); q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END S_R74194 ;ARCHITECTURE bhv OF S_R74194 IS SIGNAL tmp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk,clrn) BEGIN IF(clrn=0)THEN tmp=0000 ; ELSIF(clkEVENT AND clk=1)THEN IF(ss=11)THEN tmp=din ; ELSIF(ss=01)THEN tmp=srsi&tmp (3 downto 1) ; ELSIF(ss=10)THEN tmp=tmp (2 downto 0)&slsi ; END IF; END IF; q=tmp ; END PROCESS; END bhv; （2）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY S_C74161 IS PORT(clk, ldn,clrn,enp,ent: IN STD_LOGIC; din:IN STD_LOGIC_VECTOR(3 DOWNTO 0); q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; rco: OUT STD_LOGIC );END S_C74161 ;ARCHITECTURE behav OF S_C74161 IS SIGNAL tmp: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN PROCESS(clk, clrn) BEGIN IF clrn = 0 THEN tmp= 0000 ; ELSIF (clkEVENT AND clk = 1) THEN IF ldn=0 THEN tmp =din ; ELSIF (enp=1and ent =1) THEN tmp = tmp +1 ; END IF; END IF; q= tmp ; END PROCESS; rco = tmp (3) and tmp (2) and tmp (1) and tmp (0) and ent; END behav; 2.试给出一位全减器的算法描述、数据流描述、结构描述和混合描述（1）算法描述 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALLENTITY f_sub ISPORT(x,y,sub_in:IN STD_LOGIC;sub_out,diff:OUT STD_LOGIC);END f_sub ;ARCHITECTURE bhv OF f_sub ISSIGNAL tmp:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN tmp diff=0;sub_out diff=1;sub_out diff=1;sub_out diff=0;sub_out diff=1;sub_out diff=0;sub_out diff=0;sub_out diff=1;sub_out NULL; END CASE; END PROCESS;END bhv ；（2）数据流描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALLENTITY f_sub ISPORT(x,y,sub_in:IN STD_LOGIC;sub_out,diff:OUT STD_LOGIC);END f_sub ;ARCHITECTURE rtl OF f_sub ISBEGIN diff=x XOR y XOR sub_in; sub_out=(NOT x AND y )OR (x XNOR y) AND sub_in);END rtl ; （3）结构描述-半加器描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY h_sub ISPORT(a,b:IN STD_LOGIC; co,so:OUT STD_LOGIC);END h_sub ;ARCHITECTURE fh1 OF h_sub ISBEGIN so=a XOR b; co=NOT a AND b; END fh1; -或门描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY or2a ISPORT(a,b:IN STD_LOGIC; c:OUT STD_LOGIC);END or2a;ARCHITECTURE one OF or2a ISBEGINc=a OR b; END one;-全减器描述LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY f_sub1 IS PORT(x,y,sub_in:IN STD_LOGIC; sub_out,diff:OUT STD_LOGIC);END f_sub1 ;ARCHITECTURE strl OF f_sub1 IS COMPONENT h_sub PORT(a,b:IN STD_LOGIC; co,so:OUT STD_LOGIC); END COMPONENT; COMPONENT or2aPORT(a,b:IN STD_LOGIC; c:OUT STD_LOGIC); END COMPONENT; SIGNAL d,e,f:STD_LOGIC;BEGIN u1:h_sub PORT MAP(x,y,d,e); u2:h_sub PORT MAP(e,sub_in,f,diff); u3:or2a PORT MAP(d,f,sub_out); END strl ; 3. 用VHDL语言设计实现输出占空比为50%的1000分频器。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDIV_1000ISPORT(CLK,CLR:INSTD_LOGIC;DIV:OUTSTD_LOGIC);END;ARCHITECTUREAOFDIV_1000ISSIGNALQ:STD_LOGIC;BEGINDIV=Q;PROCESS(CLK,CLR