信息工程专业英语翻译论文.doc

信息工程专业英语题目：未来宽带网络的高性能住宅网关学 院：信息工程班 级：信工131（通信）姓 名：郑浩学 号：20131524109指导老师：张树静时 间：2016-06-29High Performance Residential Gateway for Future Broadband NetworkAbstract-with development of broadband network and rich-content services from Internet, a high performance residential gateway is required in home network. In the paper, a residential gateway (RG) is presented based on multi-core network processor and media processor. The expansibility of RG hardware is described through hardware architecture. And it outlines the architecture of RG software, which supports multi-core and multi-processor hardware. In QoS of RG，queue control and session handoff are considered. The RG will support future broadband network. Keywords-Home Network; Residential Gateway(RG); Quality of Service(QoS); Information Service; Multi-core ProcessorI. INTRODUCTION As development of broadband network and rich-content services from Internet, a high performance residential gateway is required in home network. Now, most of Internet conceptions focus on speedy network, colorful services, high performance and low cost. Many services, such as online game, Internet-TV, VoIP and VoD (Video on Demand), require network from real-time, fitter and package loss rate. A high performance residential gateway is required in home network. Comparing with other equipments of network, generally, Residential Gateway (RG) is an embedded system and has a lower hardware level. So RG becomes an important footing of multi-services network, such as telecommunication networks, TV networks and computer networks (Internet). And thin terminal impression of RG will being changed. For high performance convergence networks, RG must be available, secure, manageable and accountable. Achieve these objectives, a residential gateway (RG) is presented based on multi-core network processor and media processor in the pape, including application scenario in section II, hardware architecture in section III, software architecture in section IV and QoS thinking in section V.II. APPLICATION SCENARIO The application scenario of RG is shown in Figure 1. RG is a gateway between home network and extenal network, such as telecommunication networks, TV networks and computer networks (Internet). Though RG, wire network and wireless network is built in home network, i.e. 802.11a/b/g wireless network and 10/100/1000Base LAN. Many home facilities, such as IP STB, computer, and laptop, can connect to the LAN through wireless or wire mode. Furthermore, multi-interfaces supports automation equipment，store device, digital camera, TV and telephone. Based on the scenario, RG need support services from telecommunication networks, TV networks and computer networks (Internet), which requires many interface modes and processing capabilities. In interface modes, it should have optical fiber, coaxial cable, telephone line and so on. In processing capabilities, it should have functions of protocol adaptation, data encapsulation and data Syntax. On other hand, adapting to requirement of commercial network, RG support many key items: Security Scheme, QoS Requirement, Manageable and Accountable Scheme. Firewall based NAT technology is an important guard. Many classes of service traffic, WWW, VoIP, Video and FTP etc., converge on RG. RG must process or forward them. Considering CPUs process capability and hardware resource, such CPU mips, memory capability and forward efficiency and so on. QoS control may be hard and ingenious. QoS scheme must be simply and availably implemented. A simple DiffServ1 algorithm is placed on RG. At the management respect, RG has local or remote management functions through Web and telenet. Many functions and options are configured by them. And service provider easily carries through software updates and new services deployment. RG have a maturity database for detail tolling entries.III. HARDWARE ARCHITECTURE RG mainly consists of four modules or parts, which are NPP (Network Processing Part), Media Process Part (MPP), NAM( Network Access Module) and NPM(Normal Periphery Module). Figure 2 shows the hardware architecture of RG. RG has two main parts: NPP is mainly based on multi- core processor and MPP is mainly based on media processor. Main chip of NPP is CN3860 coming from Cavium corporation. CN3860 is Multi-core MIPS64 processors, which targets intelligent, multi-gigabit networking, control plane, storage, and wireless applications in next-generation equipment. The family includes fifteen software-compatible processors, with four to sixteen cnMIPS64 cores on a single chip that integrate next-generation networking I/Os along with the most advanced security and application hardware acceleration2.Main chip of NPP is SMP8670 coming from Sigma Designs corporation. The SMP8670 provides a highly-integrated and high-performance solution for media processing. The Secure Media Processor architecture offers advanced content protection, supporting a wide variety of Digital Rights Management (DRM) and Conditional Access (CA) solutions3. NAM supports interfaces of fiber, coaxial cable, telephone line. NPM supports interfaces of SATA, DART, USB, DDR Memory and Flash Memory. IV. SOFTWARE ARCHITECTURE RG has five modules: RTOS(Real Time Operating System )module, Network Module, BSP(Board Support Package) Driver module, MPEG Decode and VoIP module. Figure 3 shows the software architecture of RG. RTOS module has topmost control power of system resources, including hardware and software. System tasks control show RTOS power. Bus control, Memory control, TCP/IP stack, multi-services schedule is implemented on the module. Other modules communicate with the module through the event scheme. BSP Driver Module provide an interface to hardware components of NAM and NPM, i.e. Cable Tuner, Switch ,ADSL2+ PHY and other chips driver. The drivers allow the upper RTOS or applications to control hardware components. Network module contains WAN Control, LAN Control and 802.11b Control. The WAN interface ADSL2+ and Ethernet. But the system mainly uses ADSL2+ as Internet access mode. LAN Control is wire VLAN (Virtual Lan) management. 802.11b Control implements wireless LAN management and WEP. MPEG Decode Module supports MPEG 1/2/4 Decode, mainly including Interface Driver and A/V Manager. A/V Manager fulfills MPEG Decode, containing data buffer and traffic control schemes to assure QoS. Interface Driver are for IDE and USB, which supply media recording and favorite information store. VoIP Module contains Phone Interface, Signaling Control and Voice Data Control. Phone Interface provides software compo- nents that handle interface between user and ADSL2+ PHY. It implements Hook Off/On signaling handle, Tone On/Off, DTMF digits send-out and voice compression/decompression configure. The protocols, such as H.323, SIP and MGCP/H.248, are completely set on the system. Voice Stream Control mainly contains voice compression/decompression data buffer management and voice stream control through RTP and RTCP. Application Module is composed of Firewall, SNMP, QoS Manager and TFTP. Firewall with NAT provide the system security. SNMP gives a management function for MIBs(Management Information Bases). TFTP (Trivial File Transport Protocol) client is used to download upgrade or update files. CN3860 is based on multi-core and collaborative work and shared memory management, drivers, as shown in Figure 4. Discussed in more detail below shared memory management, registration and multi-function table function- calls between the CPU and other modules to achieve. Multi-core shared memory board, although some memory is used exclusively by a single CPU; virtually all of the available memory is shared memory, as shown below: (1) Some memory is given the exclusive use of CPU, which stores appropriate operating system and procedures; (2) Some memory is shared memory, to facilitate communication between CPU and provide data pipe and up the function table. And Multi-core system efficiency is closely related to the latter. The following paper discusses the main focus on the latter. Multi-core shared memory is used by the public storage. In start-up phase, it is initialized饰the CPUO. Through the submission of memory identity and size, any CPU applies for shared memory. Additional CPU can use the same memory area using identity. Probably all the CPU may also use the same memory, so both read and write are protected by hardware signals to avoid multi-core simultaneous access to shared memory. In addition, based on the shared memory of data path, the CPU can save memory and reduce memory copy, which effectively improves the efficiency of embedded systems. Shared memory up function table is for remote calls between multiple cores to provide client/server (C/S: Client /Server) call model. C/S mode realization described as follows: CPUj with realization and implementation of the function is a server, whose CPU-ID and the specific function are registered the registration function and function pointer entry in the table. CPUi which calls the function is a client, through the registration function table to call function. Client applications can be retrieved by the function name to achieve the CPU ID function and its implementation functions. With CPUj data pipeline, parameters can been passed to CPUj.If the called function has the results back to the CPUi, they can be passed back using CPUi data pipeline. Functions registered on the server has an indirect blocking mode and indirect non-blocking mode. In the indirect blocking mode, the client need to get return values from the server, that is, the caller must wait until the process is finished. Before performing this function, the caller is blocked. The configuration function with the return value is called as indirect block function. In indirect non-blocking mode, client calls the server, which does not need to obtain the return value. CPUO is registered in the function table Demo()function, so CPUO a server, Multi-core provides the printf()service. Allocated from the function table Demo()，CPU 1 indirectly called Demo()function, which as a client. When the server performs the function, if the function call on CPUO function modules, such as printf()function, the corresponding characters will be displayed on the console output, called an indirect non-blocking calls. If you need to perform a function with return value, CPU 1 Data access will be through the return value to return, and CPU1 need to wait for the return value, called the indirect blocking call. Multi-core communication signals between the memory sharing mechanism is an important foundation for achieving the main way to achieve this through an interrupt mechanism to ensure real-time information and data exchange requirements, which is referred to as the processor to the processor interrupt (PTP: Processor-to -Processor) interrupt. PTP CPU interrupt occurs between the source and target CPU, in which the purpose are: (1) The source and target CPUs, can use the CPU data path (shared memory) to exchange data, reducing memory copies and improving the efficiency of the system, especiallythe large quantities of network data, such as the exchange between CPUO and CPU1 Network packets, CPU2 and CPU1 exchange between the real-time voice data. (2) to achieve that the target CPU executes the function which the source CPU calls, which achieves parallel processing system CPU, which greatly improves system efficiency.V. QOS THINKING QoS thinking should be systemic and detailed. From protocol layers, QoS control focuses on the IP layer, which does justice to TCP and UDP data. For the stream QoS trait, QoS thinking brandwith, fitter, data duration, data quantity ,delay, client sensitivity of QoS, etc. Simple WFQ56(Weight Fair Queueing) algorithm is implemented on the system, including two stages. First stage, multi-services start-up, the service priority (weight) is fixed. The Order of priority is Voice data, A/V data and other data service from higher to lower level. Second stage, multi- services full-work, the service priority (weight) is self- adaptive, thinking over occupancy buffer quantity, real-time trait, burst data quantity and burst period. Through NS2 simulation, the system shows preferable QoS property. Session handoff control module including information collector, arbiter, session trigger and handoff task manager, as shown in Figure 5. Information collector is responsible for sharing information collection, which polls session handoff-related information, such information includes network information, user information and sensor information. RG and WLAN network information is the connection between the state, performance and the current session of the network connection, such as WLAN or GPRS. User information is user set handoff threshold, the priority of access networks and so on. Sensor information is the use of position sensor information as a condition of the trigger switch (extended support). The arbiter is responsible for the information providing under the Information collector, weigh the user settings, network performance and service quality, the formation of arbitration whether to switch, switch mode (handoff is GPRS or WLAN to GPRS to WLAN handoff). Trigger responsible for the arbitration session, the result of the formation of the instruction sessions, instructions to handoff UA(User Agent) moves into the switching process. Handoff Task Manager - Control Module as the core handoff control to ensure the information collector, arbiter and session trigger work together. VI. CONCLUSION The paper presents the design and analysis of Residential Gateway. It supplies a total solution to the digital home network. For detail security, management and QoS thinking, RG can be adapted Future Broadband Network. REFERENCES1IETF working group on DifferentiateService.http:/www.iet#org/html.charters/diffserv-charter.html2Cavium Network OCTEON CN38XX Hardware Reference Manual,/OCTEON_ CN38XX CN36XX.ht ml3Sigma Designs SMP8670 Datasheet,/media _processor_overview.php4A.K. Parekh and R.G. Gallager. A gene-ralized processor sharing approach to flow control in integrated services networks: The multiple node case. IEEE/ACM Transactions on the Networking, Vo1.2,No.2,pp:137150, Apr.19945Barry Luong, Evaluation Modeling In Performance and Resource Allocation for Restidential Broadband Gatways,Califomia State University,Long Beach,2003未来宽带网络的高性能住宅网关摘要：随着宽带网络的发展和互联网上丰富的内容服务，家庭网络需要一个高性能的住宅网关。在本文中，住宅网关（RG）是基于多核网络处理器和媒体处理器介绍。RG硬件的可扩展性是通过硬件体系结构描述。它概述了该软件的体系结构，它支持多核多处理器硬件。在QoS的RG，考虑队列控制和会话切换。RG将支持未来的宽带网络。关键词家庭网络；住宅网关（RG）；服务质量（QoS）；信息服务；多核心处理器一、引言随着宽带网络的发展和互联网上丰富的内容服务，家庭网络需要一个高性能的住宅网关。现在，大多数互联网概念专注于快速的网络，丰富多彩的服务，高性能和低成本。许多服务，如在线游戏、网络电视、VOIP和VOD（视频点播），要求网络的实时、钳工和包丢失率。家庭网络中需要一个高性能的住宅网关。与网络中的其他设备，一般来说，住宅网关（RG）是一个嵌入式系统具有较低的硬件水平。所以RG成为多服务网络的重要基础，如电信网、电视网和计算机网（互联网）。和RG瘦终端的印象将被改变。对于高性能的融合网络，RG必须是有效的，安全的，可管理的和负责任的。实现这些目标，住宅网关（RG）是基于本文提出的多核网络处理器和媒体处理器，包括在第二节中的应用场景，在第三部分的硬件结构、软件体系结构、QoS在第四节的思考。二、 应用场景RG的应用场景如图1所示。RG是家庭网络和外部网络之间的网关，如电信网、电视网和计算机网（互联网）。虽然RG，有线网络和无线网络是建立在家庭网络，即802.11a/b/g无线网络和10 / 100 / 1000base局域网。许多家庭设施，如IP机顶盒、电脑和笔记本电脑，可以连接到局域网，通过无线或有线方式。此外，多接口支持自动化设备，存储设备，数码相机，电视和电话。基于情景，RG需要支持服务的电信网、电视网和计算机网（互联网），这需要很多的接口方式和处理能力。在接口模式中，应具有光纤、同轴电缆、电话线等。在处理能力方面，它应该具有协议适应、数据封装和数据语法的功能。另一方面，适应商业网络要求，RG支持许多关键项目：安全方案，QoS要求，管理和负责的方案。基于NAT技术的防火墙是一个重要的保护。许多类业务服务、WWW、VoIP、视频、FTP等，聚集在RG。RG必须处理或转发。考虑到CPU处理能力和硬件资源，如CPU的MIPS，记忆能力和推进效率等。服务质量控制可能是硬而巧妙的。服务质量方案必须简单有效地实现。一个简单的区分【1】算法放在RG。在管理方面，RG的本地或远程通过Web和远程管理功能。许多功能和选项是由他们配置的。和服务提供商很容易进行软件更新和新的服务部署。RG有详细收费项目成熟的数据库。三、硬件架构RG主要分为四大模块或部件，这是NPP（网络处理部分），媒体处理部分（MPP）、越南（网络接入模块）和NPM（正常的外围模块）。图2显示了RG的硬件体系结构。RG有两个主要部分：NPP主要是基于多核处理器和MPP主要是基于媒体处理器。核电站的主芯片是cn3860来自Cavium公司。cn3860是多核MIPS64处理器，它的目标智能，多千兆网络，控制平面，存储，和下一代设备的无线应用。家庭包括十五软件兼容的处理器，四到十六cnmips64内核在一个芯片上集成的下一代网络I/O以及最先进的安全和应用的硬件加速 2 。核电站的主芯片是smp8670来自Sigma Designs公司。的smp8670提供高度集成和高性能的解决方案，媒体处理。安全媒体处理器体系结构提供了先进的内容保护，支持多种数字版权管理（DRM）和条件接收（CA）解决方案 3 。不支持光纤接口，同轴电缆，电话线。NPM支持SATA、飞镖、USB接口、DDR内存和闪存。四、软件体系结构RG五模块：RTOS（实时操作系统）模块、网络模块、BSP（板级支持包）驱动模块、MPEG解码和语音模块。图3显示了RG的软件体系结构。实时操作系统模块具有系统资源的最高控制权，包括硬件和软件。系统任务的控制显示系统电源。总线控制、存储控制、TCPIP协议栈，多服务调度模块上的实现。其他模块通过事件方案与模块进行通信。BSP驱动模块NAM和NPM的硬件组件提供的接口，即有线电视调谐器，开关，ADSL2 + PHY和其它芯片的驱动程序。司机让上实时操作系统或应用程序控制的硬件组件。网络模块包含广域网控制、局域网控制和802.11b的控制。广域网接口和以太网ADSL2+。但该系统主要采用ADSL2+作为互联网接入方式。局域网控制VLAN（虚拟局域网）管理线。802.11b无线局域网的管理和控制实现了WEP。MPEG解码模块支持MPEG 1 / 2 / 4解码，主要包括接口驱动和A / V经理。的A / V经理实现MPEG解码，包含数据的缓冲区和交通控制方案，保证服务质量。IDE和USB接口驱动，提供记录和喜爱的信息存储媒体。VoIP电话接口模块包含控制和语音信号，数据控制。电话接口提供软件复制-相关的因素，处理用户界面和物理之间的ADSL2 +。它执行钩了/我们信号处理，音/关闭，发送DTMF数字语音压缩/解压出和配置。the协议，如SIP和MGCP和H.248协议H.323，are completely set on the系统。语音流控制主要包含语音压缩/解压数据缓冲区管理和控制通过RTP和RTCP声音流。应用模块是由防火墙、SNMP、QoS管理和TFTP。防火墙与NAT提供制度保障。SNMP MIB给出了一个管理功能（管理信息库）。TFTP（简单文件传输协议）客户端来下载升级或更新文件。CN3860基于多核的协同工作和共享内存管理，驱动程序，如图4所示。讨论了在更详细的下面共享内存管理，注册和多功能表功能-调用之间的中央处理器和其他模块的实现。多核心共享内存板，虽然一些内存是专门由一个单一的中央处理器，几乎所有可用的内存共享内存，如下图所示：（1）一些内存是给定的专用使用的中央处理器，它存储适当的操作系统和程序；（2）内存是共享内存，便于中央处理器之间的通信，并提供数据管和上下功能表。和多核心系统效率是密切相关的。下面的文章讨论了后者的主要焦点。公共存储使用多核心共享内存。在启动阶段，它被初始化饰的cpuo。通过提交内存的身份和大小，任何一种处理器都适用于共享内存。额外的处理器可以使用相同的内存区域使用身份。可能所有的处理器也可以使用相同的内存，所以无论是读和写是受保护的硬件信号，以避免多核同时访问共享内存。此外，基于数据路径的共享内存，可以节省内存和减少内存拷贝，有效地提高了嵌入式系统的效率。共享内存功能表是为多个核心之间的远程调用提供客户