基于ARM7与FPGA的多路时序控制系统-FPGA模块设计程序.docx

程序1 .FPGA与ARM7的串口通信程序module PC104_EP1C12(clk_i0, /7.68Mclk_i1, /40M rst_i, /外部复位输入（FPGA 240脚）/-/MCUmcu_dat, /计算机数据位（DB0-DB7）mcu_adr, /计算机地址位（AB0-AB5）mcu_rd, /计算机读 （PC104的NIOR信号）mcu_wr, /计算机写 （PC104的NIOW信号） mcu_cs, /计算机片选（PC104的AEN信号）/-/LED,led, /61 PIN/-/FIFOfifo_dat, /FIFO 数据24位fifo_wr,/ FIFO 写fifo_ef,fifo_hf,fifo_ff, /FIFO 空 半满 满信号fifo_reset, /FIFO复位 ，数据清空fifo_rd1, /低16位读，fifo_rd2, /高16位读，/-/test pointt1,t2,t3,t4,t5,t6,t7,t8,t9, /测试点TP1-TP9initd,);/-input clk_i0, clk_i1 ;input rst_i ;input initd;/-inout 7:0mcu_dat;input 5:0 mcu_adr ;inputmcu_rd;inputmcu_wr;inputmcu_cs;wire mcu_cs;/-output t1,t2,t3,t4,t5,t6,t7,t8;input t9;/-output23:0 fifo_dat; /FIFO 数据24位outputfifo_wr;/ FIFO 写input fifo_ef,fifo_hf,fifo_ff; /FIFO 空 半满 满信号outputfifo_reset; /FIFO复位 ，数据清空outputfifo_rd1; /低16位读，outputfifo_rd2; /高16位读，wire 2:0 fifo_status; /FIFO状态寄存器reg 7:0 mcu_dat_i;reg 23:0 fifo_dat_i;reg fifo_reset_i;reg 23:0 fifo_counter; /FIFO计数器24位reg 7:0 reg_test,reg_test2; /测试寄存器reg 7:0 reg_counter; /测试计数器output led;reg fifo_wr_clk;wirereset = rst_i;wire 2:0 statu;wire clk;assign clk = clk_i1;assign led = fifo_ff;assign t3 = fifo_rd1;assign t6 = fifo_rd2;assign fifo_status0 = fifo_ef;assign fifo_status1 = fifo_hf;assign fifo_status2 = fifo_ff;assign fifo_wr = fifo_wr_clk;assign fifo_reset = fifo_reset_i & reset ; /命令控制或复位控制FIFO 清空assign fifo_rd1 = mcu_rd | mcu_cs | (mcu_adr5:0!=6h00 );/读取15:0位FIFO数据assign fifo_rd2 = mcu_rd | mcu_cs | (mcu_adr5:0!=6h02 );/读取23:16位FIFO数据assign mcu_dat = (mcu_rd | mcu_cs) ? 16hzzzz : mcu_dat_i; /读取FPGA的8位数据assign fifo_dat = (fifo_wr )? 24hzzzzzz : fifo_dat_i;/=/组合逻辑/处理ARM读FPGA 8位寄存器always (mcu_rd or mcu_adr or mcu_cs)beginif(mcu_cs = 1b0) & (mcu_rd=1b0)/AEN 及NIOR 同时产生case (mcu_adr5:0)6h30: mcu_dat_i2:0 = fifo_status2:0 ; /fifo 状态6h32: mcu_dat_i = reg_counter ;6h34: mcu_dat_i = reg_test ;6h38: mcu_dat_i = reg_test2;endcaseelse beginmcu_dat_i = 6hzz;endend/=/处理ARM写FPGA 8位寄存器always (mcu_wr or mcu_adr or mcu_cs)beginif(mcu_cs = 1b0) & (mcu_wr=1b0) /AEN 及NIOW 同时产生case (mcu_adr5:0)6h32: reg_counter = mcu_dat;6h34: reg_test = mcu_dat;6h38: reg_test2 = mcu_dat;6h3a: fifo_reset_i = mcu_dat;endcaseelse mcu_dat_i = 6hzz;end/=/ 时序逻辑/FIFO写时钟分频到500HZreg 15:0 cnt;always(posedge clk_i1 or negedge reset)begin if ( reset ) cnt = #1 16h0000;else if (clk_i1) begincnt = cnt +1 ;if (cnt=16d80000) beginfifo_wr_clk = fifo_wr_clk; /40000000 / 800000 x2 = 1000HZcnt = 16h0000;endendend/-/ 将24位计数器的值写入FIFO always(posedge fifo_wr_clk or negedge reset)begin if ( reset ) fifo_counter = #1 24h000000;else if (fifo_wr_clk) beginfifo_dat_i = fifo_counter;fifo_counter = fifo_counter + 1; endend/=Endmodule2.延迟模块程序：/ 实现20个延迟信号module delay_20;reg 7:0 delay1 , delay2 , delay3 , delay4 , delay5 , delay6 , delay7 , delay8 , delay9 , delay10, delay11, delay12, delay13, delay14, delay15, delay16, delay17, delay18, delay19, delay20; / 定义20个寄存器，存储变量reg delay_en, load, clock;reg de1 ,de2 ,de3 ,de4 ,de5 ,de6 ,de7 ,de8 ,de9 ,de10,de11,de12,de13,de14,de15,de16,de17,de18,de19,de20; / 具体的改变值 always #5 clock = clock; / 时钟信号initial begindelay1 = 8d1 ;delay2 = 8d2 ;delay3 = 8d3 ;delay4 = 8d4 ;delay5 = 8d5 ;delay6 = 8d6 ;delay7 = 8d7 ;delay8 = 8d8 ;delay9 = 8d9 ;delay10 = 8d10;delay11 = 8d11;delay12 = 8d12;delay13 = 8d13;delay14 = 8d14;delay15 = 8d15;delay16 = 8d16;delay17 = 8d17;delay18 = 8d18;delay19 = 8d19;delay20 = 8d20; / 初始化clock = 0;delay_en = 0;load = 0;#5 load = 1; #10 load = 0; / 延迟出现波形#10 delay_en = 1;endinitial beginde1 = 0;de2 = 0;de3 = 0;de4 = 0;de5 = 0;de6 = 0;de7 = 0;de8 = 0; de9 = 0;de10 = 0;de11 = 0;de12 = 0;de13 = 0;de14 = 0;de15 = 0;de16 = 0;de17 = 0;de18 = 0;de19 = 0;de20 = 0; / 初始化#50 ; de1 = 1;#10; de2 = 1;#10; de3 = 1;#10; de4 = 1;#10; de5 = 1;#10; de6 = 1;#10; de7 = 1;#10; de8 = 1;#10; de9 = 1;#10; de10 =