FPGA verilog LCD12864显示程序.doc

module lcd12864(LCD_RST,PSB,clk, rs, rw, en,dat);output reg LCD_RST;output reg PSB;input clk; output 7:0 dat; output reg rs,rw,en; /tri en; reg e; reg 7:0 dat; reg 31:0 counter=0; reg 6:0 current=0,next=0; reg clkr; reg 31:0 cnt=0; parameter set0=6h0; parameter set1=6h1; parameter set2=6h2; parameter set3=6h3; parameter set4=6h4; parameter set5=6h5; parameter set6=6h6; parameter dat0=6h7; parameter dat1=6h8; parameter dat2=6h9; parameter dat3=6hA; parameter dat4=6hB; parameter dat5=6hC; parameter dat6=6hD; parameter dat7=6hE; parameter dat8=6hF; parameter dat9=6h10; parameter dat10=6h12; parameter dat11=6h13; parameter dat12=6h14; parameter dat13=6h15; parameter dat14=6h16; parameter dat15=6h17; parameter nul=6h18; parameter bai=8h31;parameter shi=8h30;parameter ge=8h30; always (posedge clk) /da de shi zhong pinlv begin counter=counter+1; if(counter=32h1FFFE) begin counter=0; end else if(counter=32h20) begin/(counter=32h57FE) clkr=clkr; enden=clkr|e; rw=0; LCD_RST=1b1;PSB=1b1;end always (posedge clk) begin if(counter=32h20)begin /counter=32haff0 current=next; case(current) set0: begin rs=0; dat=8h30; next=set1; end set1: begin rs=0; dat=8h0c; next=set2; end set2: begin rs=0; dat=8h6; next=set3; end/ set3: begin rs=0; dat=8h1; next=dat0; end dat0: begin rs=1; dat=F; next=dat1; end /? dat1: begin rs=1; dat=r; next=dat2; end dat2: begin rs=1; dat=q; next=dat3; end dat3: begin rs=1; dat=u;next=dat4; end dat4: begin rs=1; dat=e; next=dat5; end dat5: begin rs=1; dat=n; next=dat6; end dat6: begin rs=1; dat=c; next=dat7; end dat7: begin rs=1; dat=y;next=dat8; end dat8: begin rs=1; dat=:; next=set6; end set6: begin rs=0; dat=8h90; next=dat9;end dat9: begin rs=1; dat=bai; next=dat10; end /? dat10: begin rs=1; dat=shi; next=dat11; end dat11: begin rs=1; dat=ge; next=dat12; end dat12: begin rs=1; dat= ;next=dat13; end dat13: begin rs=1; dat=k; next=dat14; end dat14: begin rs=1; dat=H; next=dat15; end dat15: begin rs=1; dat=z; next=nul; end nul: begin rs=0; dat=8h00; / ?E ? ? if(cnt!=2h2) begin e=0;current=set0