SONY CDX-4280汽车音响电路图纸.pdf

1 Model Name Using Similar MechanismCDX 4180 CD Drive Mechanism TypeMG 363X 121 Optical Pick up NameKSS 521A SERVICE MANUALE Model CDX 4280 FM AM COMPACT DISC PLAYER MICROFILM CD player section SystemCompact disc digital audio system Signal to noise ratio90 dB Frequency response10 20 000 Hz Wow and flutterBelow measurable limit Tuner section FM Tuning rangeFM tuning interval 50 kHz 200 kHz switchable 87 5 108 0 MHz at 50 kHz step 87 5 107 9 MHz at 200 kHz step Antenna terminalExternal antenna connector Intermediate frequency10 7 MHz Usable sensitivity8 dBf Selectivity75 dB at 400 kHz Signal to noise ratio65 dB stereo 68 dB mono Harmonic distortion at 1 kHz 0 5 stereo 0 3 mono Separation35 dB at 1 kHz Frequency response30 15 000 Hz Capture ratio2 dB AM Tuning rangeAM tuning interval 9 kHz 10 kHz switchable 531 1 602 kHz at 9 kHz step 530 1 710 kHz at 10 kHz step Antenna terminalExternal antenna connector Intermediate frequency10 71 MHz 450 kHz Sensitivity30 V SPECIFICATIONS Power amplifier section OutputsSpeaker outputs sure seal connectors Speaker impedance4 8 ohms Maximum power output40 W 4 at 4 ohms General OutputsLine outputs 2 Power antenna relay control Power amplifier control lead Telephone ATT control lead Tone controlsBass 10 dB at 100 Hz Treble 10 dB at 10 kHz Power requirements12 V DC car battery negative ground DimensionsApprox 178 50 185 mm w h d Mounting dimensionsApprox 182 53 162 mm w h d MassApprox 1 2 kg Supplied accessoriesParts for installation and connections 1 set Front panel case 1 Design and specifications are subject to change without notice 19 4 1 IC PIN DESCRIPTION IC801 PD17705GC 526 3B9 SYSTEM CONTROL Pin No Pin NameI OPin Description 1SIRCSISIRCS input A D 2IN SWICD mechanism position detection 3D SWICD mechanism position detection 4SELF SWICD mechanism position detection 5L SWILIMIT switch 6LM EJOLoading motor control Eject direction 7LM LODOLoading motor control Loading direction 8ANT ONOPower control for amplifier 9MONOOForce MONO output 10SDISD signal input 11BAND SWIBand plan setting of general area 12AREA1 SWIDestination select 1 Fixed at L 13AREA2 SWIDestination select 2 Fixed at H 14 15RE1 2IRotary encoder input 1 2 16SEEKOSEEK output 17 20NC Not used 21GND3 GND 22 24KEYIN3 1IA D key input 3 1 25ROT INIRotary commander input 26S METERIFM and AM common signal meter A D conversion input 27TEST SWITEST mode select input 28AM IFCIAM center frequency input 29FM IFCIFM center frequency input 30VDD2 Power supply 5 V 31VCOH FMILocal oscillation frequency input FM 32VCOL AMILocal oscillation frequency input AM 33GND2 GND 34NC Not used 35EO1 PDOUTOError out output 36TESTO Fixed at L 37AM ON TU ON OAM power output AM select 38FM ON FM AM OFM power output FM select 39LCL DXOLOCAL DX select H LOCAL L DX 40BEEPOBEEP output 41ACC INIAccessory input 42SCORISUBQ data read request 43MUTEOSystem mute output 44AMP MUTEOPower amplifier mute output 45TEL MUTEOTelephone mute output 46NC Not used 47VOL CEOElectric volume chip select 48VOL CLKOElectric volume serial clock 49VOL DATAOElectric volume serial data 50EMPHOODe emphasis control output 51PW ONOSystem power control 52MD ONOLoading motor power 53CD ONOServo drive power 54ILL ONOIllumination output 55 56MOD1 2OBus boost control 1 2 57NC Not used 58LCD CEOLCD drive chip select output SECTION 4 DIAGRAMS 20 Pin No Pin NameI OPin Description 59EZ SELISHIFT input 60SENSIInformation input from servo IC 61FOKIFocus OK input 62LD ONOLaser diode control 63NC Not used 64ST MONOI OUsed for both STEREO indicator display input and force MONO output FM 65LCD CKOOLCD driver serial clock output 66LCD SOOLCD driver serial data output 67C ALARMOCaution alarm output 68SQ CKOOQ data read serial clock output 69CD RSTOServo IC DAC reset output 70SQ SIIQ data input 71CD SOOSerial data output to servo IC 72CD LATOData latch output to servo IC 73CD CKOOSerial clock output to servo IC 74VREF Not used 75GND1 GND 76X OUTOCrystal oscillator connection 4 5 MHz 77X INICrystal oscillator connection 4 5 MHz 78BU INIBack up detection 79VDD1 Power supply 5 V 80RESETIRESET input 4 4 SCHEMATIC DIAGRAM CD MECHANISM SECTION Refer to page 22 for Waveforms and Note and page 37 for IC Block Diagrams CDX 4280 1 2 25 26 Page 33 Note All capacitors are in F unless otherwise noted pF F 50 WV or less are not indicated except for electrolytics and tantalums All resistors are in and 1 4 W or less unless otherwise specified U B Line Power voltage is dc 14 4V and fed with regulated dc power supply from ACC and BATT cords C panel designation Voltage is dc with respect to ground under no signal detuned condition no mark FM Voltages are taken with a VOM Input impedance 10 M Voltage variations may be noted due to normal production tolerances 4 6 SCHEMATIC DIAGRAM DISPLAY SECTION CDX 4280 29 30 Page 36 CDX 4280 Note All capacitors are in F unless otherwise noted pF F 50 WV or less are not indicated except for electrolytics and tantalums All resistors are in and 1 4 W or less unless otherwise specified internal component C panel designation U B Line Power voltage is dc 14 4V and fed with regulated dc power supply from ACC and BATT cords Voltage is dc with respect to ground under no signal detuned condition no mark FM AM CD PLAY Impossible to measure Voltages are taken with a VOM Input impedance 10 M Voltage variations may be noted due to normal production tolerances Signal path F FM f AM J CD 4 8 SCHEMATIC DIAGRAM MAIN SECTION 1 2 Refer to page 39 for IC Block Diagrams ASSY 33 34 Page 26 Page 35 CDX 4280 4 9 SCHEMATIC DIAGRAM MAIN SECTION 2 2 Refer to page 34 for Note and page 39 for IC Block Diagrams 35 36 Page 29 Page 34 37 IC Block Diagrams IC1 CXD2507AQ IC3 BA6796FP T1 XLON SPOD SPOC SPOB SPOA CLKO VDD CNIN SEIN CLOK XLAT XLTO DATO 52535455565758596061626364 51 SERVO AUTO SEQUENCER 33 34 35 36 37 38 39 40 41 42 43 45 46 47 48 49 50 44 DATA XRST SENS MUTE SQCK SQSO EXCK SBSO SCOR VSS WFCK EMPH DOUT C4M FSTT XTSL XTAO XTAI MNTO 20 21 22 23 24 25 26 2729 30 31 3228 LRCK PCMD BCLK GTOP XUGF XPCK VDD GFS RFCK C2PO XROF MNT3 MNT1 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 13 14 15 FOK MON MDP MDS LOCK TEST FILO FILI PCO VSS AVSS CLTV AVDD RF BIAS ASYI ASYO ASYE WDCK 5 14 CPU INTERFACE SUB CODE PROCESSOR DIGITAL CLV EFM DEMODULATOR DIGITAL PLL ASYMMETRY CORRECTOR 5 D A INTERFACE ERROR CORRECTOR 3 6 3 16K RAM DIGITAL OUT CLOCK GENERATOR 4 1234567891011121314 OPOUT CH4 IN CH4 CTL1 CTL2 FWD REV TRAY GND CH3 CH5 COM CH4 CH3 CH3 IN CH3 VREF CH2 CH2 IN VCC VCC CH1 CH2 CH1 IN OP IN CH1 CH1 OP IN CH2 DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER DRIVE BUFFER LEVEL SHIFT LEVEL SHIFT LEVEL SHIFT LEVEL SHIFT THERMAL SHUT DOWN 1516171819202122232425262728 LOGIC CTL1CTL2FWDREV V I 38 IC2 CXA1782BQ 363534333231302928272625 24 23 22 21 20 19 18 17 16 15 14 13 121110987654321 37 38 39 40 41 42 43 44 45 46 47 48 PHD 2 PHD 1 PHD LD RF O RF I CP CB CC1 CC2 FOK SENS C OUT XRST DATA XLT CLK VCC ISET SL O SL M SL P TA O TA M FSET TG2 TGU SRCH FE O FLB FGD FDFCT FE M FEI FEO FE BIAS F E EI VEE TED LPFI TEI ATSC TZC TDFCT VC APC LEVEL S FOK MIRR RF IV AMP1 RF IV AMP2 FE AMP TTL IIL FZC COMP DFCT IIL TTL IIL DATA REGISTER INPUT SHIFT REGISTER ADDRESS DECODER OUTPUT DECODER TTL IIL TOG1 3 BAL1 3 FS1 4TG1 2TM1 7PS1 4 F IV AMP E IV AMP BAL1 BAL2 BAL 3 TE AMP TZC COMP DFCT TM1 DFCT FS4 ATSC WINDOW COMP TOG1 TOG2 TOG3 FCS PHASE COMPENSATION FS1 F SET TG2 TM7 TM3 TM4 TM5 TM6 ISET TRACKING PHASE COMPENSATION HPF COMPLPF COMP TG1 FS2 TM2 RF M 39 IC701 SM5852FS E2 IC401 LC75374E IC702 SM5878AM E2 DECODERLATCH SHIFT REGISTER CONTROL 123456789 10 20 19 18 17 16 15 14 13 12 11 21 22 2324252627282930313233