EDA数字钟设计.doc

此文档收集于网络，如有侵权，请联系网站删除数字钟程序设计本设计在实验箱上验证，使用电路模式7，用动态扫描方式显示，“DS8使能”开关上推；动态位扫描时，时、分、秒之间间隔点亮；TMODE：12/24进制模式切换，接键8；SCAN：动态扫描时钟信号，接CLOCK0，跳线选16384Hz；MINUTE：分校时，接键1（单脉冲）；HOUR：小时时校时，接键4（单脉冲）；EXCHGE：计时/校时切换，接键5；CLK:：时钟脉冲，接CLOCK2,跳线选1Hz；RET：清零，接键7（单脉冲）；EN：计数使能，接键3；CLK1024：蜂鸣输入信号，接CLOCK5,跳线选1024Hz；SG6.0：段选信号，接PIO49到PIO43；BT7.0：位选信号，接PIO41到PIO34；SPEAKER：蜂鸣输出信号，接SPEAKER。程序模块【1】60进制模块CNT60 LIBRARY IEEE; -CLK时钟输入，RET清零，EN计数使能，USE IEEE.STD_LOGIC_1164.ALL; - CQL分或秒的个位输出，USE IEEE.STD_LOGIC_UNSIGNED.ALL; -CQH分或秒的十位输出,ENTITY CNT60 IS - COUT1进位输出PORT (CLK,RST,EN : IN STD_LOGIC;CQL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CQH: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT1 : OUT STD_LOGIC); -向外部的进位END CNT60;ARCHITECTURE behav OF CNT60 ISSIGNAL CQI0: STD_LOGIC_VECTOR (3 DOWNTO 0);SIGNAL CQI1: STD_LOGIC_VECTOR (3 DOWNTO 0);SIGNAL COUT0 : STD_LOGIC; -低位向高位的进位BEGIN PROCESS(CLK,RST,EN) -十进制BEGINIF RST=1 THEN CQI0 0);ELSIF CLKEVENT AND CLK=1 THENIF EN =1 THENIF CQI0 9 THEN CQI0 =CQI0+1;ELSE CQI0 0);END IF;END IF;IF CQI0 = 9 THEN COUT0 = 1;ELSE COUT0=0;END IF;END IF;END PROCESS;CQL=CQI0;PROCESS(COUT0,RST) -六进制BEGINIF RST=1 THEN CQI1 0);ELSIF COUT0EVENT AND COUT0=1 THENIF CQI15 THEN CQI1=CQI1+1;ELSE CQI10);END IF;IF CQI1=5 AND CQI0=9 THEN COUT1=1;ELSE COUT1=0;END IF;END IF;END PROCESS;CQH=CQI1;END behav;【2】24|12进制模块CNT24 LIBRARY IEEE; -CLK输入分的进位信号，RET清零，EN计数使能,USE IEEE.STD_LOGIC_1164.ALL; -MODE为12和24进制的切换，USE IEEE.STD_LOGIC_UNSIGNED.ALL; - CQL小时的个位输出，CQH小时的十位输出ENTITY CNT24 ISPORT (CLK,RST,EN,MODE: IN STD_LOGIC;CQL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CQH: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END CNT24;ARCHITECTURE behav OF CNT24 ISSIGNAL CQI0: STD_LOGIC_VECTOR (3 DOWNTO 0);SIGNAL CQI1: STD_LOGIC_VECTOR (3 DOWNTO 0);SIGNAL CQI2: STD_LOGIC_VECTOR (3 DOWNTO 0);SIGNAL CQI3: STD_LOGIC_VECTOR (3 DOWNTO 0); BEGINP1: PROCESS(CLK,RST,EN) -24进制模式 BEGIN IF RST=1 THEN CQI0 0);CQI1 0); ELSIF CLKEVENT AND CLK=1 THEN IF EN =1 THEN IF CQI12 THEN IF CQI09 THEN CQI0=CQI0+1;ELSE CQI00);CQI1=CQI1+1;END IF;ELSIF CQI03 THENCQI0=CQI0+1;ELSE CQI00);CQI10); END IF; END IF; END IF; END PROCESS P1; P2: PROCESS(CLK,RST,EN) -12进制模式 BEGIN IF RST=1 THEN CQI2 0);CQI3 0); ELSIF CLKEVENT AND CLK=1 THEN IF EN =1 THEN IF CQI31 THEN IF CQI29 THEN CQI2=CQI2+1;ELSE CQI20);CQI3=CQI3+1;END IF;ELSIF CQI22 THENCQI2=CQI2+1;ELSE CQI2=0001;CQI30);END IF; END IF; END IF; END PROCESS P2; P3: PROCESS(MODE) -MODE=1为24进制，MODE=0为12进制 BEGIN CASE MODE IS WHEN 1= CQL=CQI0;CQH CQL=CQI2;CQHNULL; END CASE; END PROCESS P3;END behav;【3】控制逻辑模块CONTROL LIBRARY IEEE; -EXCHGE校时与计时模式控制，USE IEEE.STD_LOGIC_1164.ALL; -MINUTE手动分校时USE IEEE.STD_LOGIC_UNSIGNED.ALL; -HOUR手动时校时ENTITY CONTROL IS -CY0,CY1分别接受秒和分的进位信号PORT (MINUTE,HOUR,EXCHGE,CY0,CY1: IN STD_LOGIC; -CLK0,CLK1分别控制分和小时的时钟脉冲CLK0: OUT STD_LOGIC;CLK1: OUT STD_LOGIC);END CONTROL;ARCHITECTURE behav OF CONTROL ISSIGNAL A0: STD_LOGIC;SIGNAL A1: STD_LOGIC;BEGINP1: PROCESS(EXCHGE,MINUTE,HOUR) BEGIN IF EXCHGE=1 THEN A0=MINUTE; A1=HOUR; END IF;END PROCESS P1;P2: PROCESS(EXCHGE,CY0,CY1) -EXCHGE=1校时模式，EXCHGE=0为计时模式 BEGIN IF EXCHGE=1 THEN CLK0=A0;CLK1=A1; ELSE CLK0=CY0;CLK1=CY1; END IF;END PROCESS P2;END ARCHITECTURE behav;【4】动态扫描模块SCAN_LED LIBRARY IEEE; -SCAN动态扫描时钟信号USE IEEE.STD_LOGIC_1164.ALL; -DIN接受时、分、秒数据USE IEEE.STD_LOGIC_UNSIGNED.ALL; -SG输出段选信号ENTITY SCAN_LED IS -输出位选信号 PORT(SCAN : IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(23 DOWNTO 0);SG:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);BT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END;ARCHITECTURE one OF SCAN_LED IS SIGNAL CNT6:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL D:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINP1:PROCESS(SCAN) BEGIN IF SCANEVENT AND SCAN=1 THEN IF CNT65 THEN CNT6=CNT6+1; ELSE CNT6 BT BT BT BT BT BT NULL; END CASE;END PROCESS P2;P4: PROCESS(CNT6) BEGIN CASE CNT6 ISWHEN000= D D D D D D NULL; END CASE; END PROCESS P4;P3:PROCESS(D) -段选 BEGIN CASE D IS WHEN 0000 =SGSGSGSGSGSGSGSGSGSGNULL; END CASE;END PROCESS P3;END ARCHITECTURE one;【5】整点报时模块ALARMLIBRARY IEEE;-ML输入分个位，MH输入分十位USE IEEE.STD_LOGIC_1164.ALL; -SL输入秒个位，SH输入秒十位USE IEEE.STD_LOGIC_UNSIGNED.ALL; -CLK输入1024Hz时钟脉冲ENTITY ALARM IS -SPEAKER输出报时信号 PORT (ML: IN STD_LOGIC_VECTOR(3 DOWNTO 0); MH: IN STD_LOGIC_VECTOR(3 DOWNTO 0); SL: IN STD_LOGIC_VECTOR(3 DOWNTO 0); SH: IN STD_LOGIC_VECTOR(3 DOWNTO 0);CLK: IN STD_LOGIC; SPEAKER: OUT STD_LOGIC);END ALARM;ARCHITECTURE behav OF ALARM ISSIGNAL DIV2CLK: STD_LOGIC;BEGIN PROCESS(CLK) BEGIN -实验箱的可用时钟有限，1024Hz作高音信号 IF CLKEVENT AND CLK=1 THEN -1024Hz时钟脉冲2分频，产生蜂鸣低音信号 DIV2CLK=NOT DIV2CLK; END IF; END PROCESS; PROCESS(MH,ML,SH,SL) BEGIN IF MH=5 AND ML=9 THEN IF SH=5 THEN IF (SL=1 OR SL=3 OR SL=5 OR SL=7) THEN -51、53、55、57秒输出低音信号 SPEAKER=DIV2CLK; ELSIF (SL=9) THEN -59秒输出高音信号 SPEAKER=CLK; ELSE SPEAKER=0; END IF; ELSE SPEAKER=0; END IF; ELSE SPEAKERCLK,RST=RST,EN=EN,COUT1=M0, CQH=D(7 DOWNTO 4),CQL=D(3 DOWNTO 0); u2: CNT60 PORT MAP(CLK=M2,RST=RST,EN=EN,COUT1=M1, CQH=D(15 DOWNTO 12),CQL=D(11 DOWNTO 8); u3: CNT24 PORT MAP(CLK=M3,RST=RST,EN=EN,MODE=TMODE, CQH=D(23 DOWNTO 20),CQL=D(19 DOWNTO 16); u4: CONTROL PORT MAP(EXCHGE=EXCHGE,HOUR=HOUR,MINUTE=MINUTE, CLK0=M2,CLK1=M3,CY0=M0,CY1=M1); u5: SCAN_LED PORT MAP(SCAN=SCAN,SG=SG,BT=BT, DIN(3 DOWNTO 0)=D(3 DOWNTO