毕业设计英文文献翻译.pdf

English literature 1 AT89C51 is a flickering 4K bytes can erase Programmable read only Memory FPEROM Erasable Programmable Read Falsh with Memory of how low voltage high CMOS8 a microprocessor chip called AT89C2051 is a flickering 2K bytes with a programmable read only memory can be erased the microcontroller The chip can erase read only memory can be erased 100 times repeatedly This device adopts ATMEL high density non volatile storage technology manufacturing and industrial standard MCS 51 instruction set and output tube JiaoXiang compatible Due to the CPU and multi function 8 bit will flash memory chips in a single ATMEL of AT89C51 is a kind of effective micro controller it is a kind of AT89C2051 streamlined version For many AT89C MCU embedded control system provides a high flexibility and inexpensive solutions 1Major features Compatible with MCS 51 4K bytes programmable flash memory Life 1000 write wipe cycle Data retention time 10 years The static job 0Hz 24Hz 3 a program memory lock 128 8 bits internal RAM 32 programmable I O 16 two timers counters Interrupt source 5 programmable serial passage The idle low power consumption and power mode Within the oscillator and clock slice 2 tube foot The VCC power supply voltage GND grounding Mouth for P0 P0 mouth open a two way leakage level I O each foot can absorb 8TTL gate current When the pipe mouth P1 first write 1 foot is defined as the high impedance input External programs can be used for P0 data storage it can be defined as the eighth data address In programming FIASH P0 mouth as the original code when FIASH input and output to calibrate the original code P0 P0 external must be pulled P1 P1 mouth is an internal provides the resistance of the eight two way I O buffers P1 mouth can receive 4TTL gate current output The one foot P1 internal and can be used for high input P1 mouth by external down for low levels will output current this is due to the internal In programming and calibration FLASH P1 mouth as eighth address receives English literature 2 P2 for an internal on mouth P2 pull up resistors of eight two way I O buffers and P2 mouth can receive output 4 TTL door mouth when the current is written P2 1 the tube feet were pulled on the internal resistance and pull as input And so as the input of tube feet were P2 external down will output current This is because the internal When used for external P2 mouth program memory or 16 bit memory address of external data access P2 mouth output address high eight In a given address 1 it is the interior and exterior when eight address data storage and mouth P2 specific functions in the output of the register contents In P2 and calibration when receiving FLASH programming high eight address signals and control signals P3 P3 mouth tube foot is 8 with internal resistance of the bidirectional I O can receive output 4 TTL gate current When P3 mouth into a 1 they are the internal and used for the high level of inputs As input due to external conditions and the low level to the output current mp3 this is due to prosper in the sake P3 mouth can also be used as anAT89C51 some special functions are shown below The foot optional function P3 0 RXD serial input P3 1 TXD serial export P3 2 INT0 external interruption 0 P3 3 INT1 1 external interruption P3 4 T0 timepiece 0 external input P3 5 T1 timepiece 1 external input P3 6 WR external data memory write for P3 7 RD external data memory read for P3 mouth as flashing programming and programming calibration receiving some control signals RST reset input When the oscillator reset device keep RST feet high level two machine cycle time ALE PROG when access to external memory address latch when the output level of allowing for latch address position bytes In programming the FLASH foot pulses used input programming In peacetime with the same frequency at ALE is the pulse signal output cycle the frequency of the oscillator frequency for six So it can resist the output pulse or external for timing But remember when used for external data storage will skip a ALE pulse If want to prohibit the ALE output can be in SFR8EH address for 0 At this time MOVX only by performing ALE MOVC instruction is S S R I S ALE In addition the foot was slightly push If the microprocessor in external executionALE the ban is invalid PSEN program memory external of communication In the external program memory refers to the period from each machine cycle PSEN twice But in the external data access memory the two effective PSEN signals will not occur EA when EA VPP keep low levels during the program memory external 0000H FFFFH whether internal program memory Note 1 encryption EA will RESET for internal lock When EA client maintain high internal procedures during storage In programming the English literature 3 FLASH on foot is used for 12V programming power VPP XTAL1 the inverting oscillator amplifier input and input to the internal clock operating circuit XTAL2 from the reverse of the output 3 oscillator features XTAL1 and XTAL2 respectively for reverse amplifier input and output The reverse amplifier can be configured to piece inside oscillator ShiJing oscillation and ceramic oscillation are adopted If use external clock source driving device XTAL2 should not meet More to the internal clock signal input to a half external clock frequency flip flop signal pulse width without any requirement but must ensure that the pulse width of the requirements of high level 4 chip erasing The PEROM array of electricity and three lock can be erased by right of control signals and keep ALE in the low level 10ms tube feet to finish In chips wipe in operation all write code array in a 1 and HeFei empty storage bytes are repeated programming before the operation must be executed In addition the steady state logic can with AT89C51 in low to zero frequency under the condition of static logic support two software can choose the model In idle mode the CPU to stop work But the RAM timer counter serial ports and interrupt system is still at work In power mode save the content and freeze RAM chips used other prohibited oscillators function until the next hardware reset English literature 4 中文科技文献 AT89C51 是 一 种 带 4K 字 节 闪 烁 可 编 程 可 擦 除 只 读 存 储 器 FPEROM Falsh Programmable and Erasable Read Only Memory 的低电压 高性能 CMOS8 位微处理器 俗称单片机 AT89C2051 是一种带 2K 字节闪烁可编程可擦除只读存储器的单片机 单片机 的可擦除只读存储器可以反复擦除 100 次 该器件采用 ATMEL 高密度非易失存储器制造技 术制造 与工业标准的 MCS 51 指令集和输出管脚相兼容 由于将多功能 8 位 CPU 和闪烁 存储器组合在单个芯片中 ATMEL 的 AT89C51 是一种高效微控制器 AT89C2051 是它的一 种精简版本 AT89C 单片机为很多嵌入式控制系统提供了一种灵活性高且价廉的方案 1 主要特性 与 MCS 51 兼容 4K 字节可编程闪烁存储器 寿命 1000 写 擦循环 数据保留时间 10 年 全静态工作 0Hz 24Hz 三级程序存储器锁定 128 8 位内部 RAM 32 可编程 I O 线 两个 16 位定时器 计数器 5 个中断源 可编程串行通道 低功耗的闲置和掉电模式 片内振荡器和时钟电路 2 管脚说明 VCC 供电电压 GND 接地 P0 口 P0 口为一个 8 位漏级开路双向 I O 口 每脚可吸收 8TTL 门电流 当 P1 口的 管脚第一次写 1 时 被定义为高阻输入 P0 能够用于外部程序数据存储器 它可以被定义 为数据 地址的第八位 在 FIASH 编程时 P0 口作为原码输入口 当 FIASH 进行校验时 P0 输出原码 此时 P0 外部必须被拉高 P1 口 P1 口是一个内部提供上拉电阻的 8 位双向 I O 口 P1 口缓冲器能接收输出 4TTL 门电流 P1 口管脚写入 1 后 被内部上拉为高 可用作输入 P1 口被外部下拉为低电平 时 将输出电流 这是由于内部上拉的缘故 在 FLASH 编程和校验时 P1 口作为第八位地 址接收 P2 口 P2 口为一个内部上拉电阻的 8 位双向 I O 口 P2 口缓冲器可接收 输出 4 个 TTL 门电流 当 P2 口被写 1 时 其管脚被内部上拉电阻拉高 且作为输入 并因此作 为输入时 P2 口的管脚被外部拉低 将输出电流 这是由于内部上拉的缘故 P2 口当用 于外部程序存储器或 16 位地址外部数据存储器进行存取时 P2 口输出地址的高八位 在 给出地址 1 时 它利用内部上拉优势 当对外部八位地址数据存储器进行读写时 P2 口输出其特殊功能寄存器的内容 P2 口在 FLASH 编程和校验时接收高八位地址信号和控制 信号 P3 口 P3 口管脚是 8 个带内部上拉电阻的双向 I O 口 可接收输出 4 个 TTL 门电流 当 P3 口写入 1 后 它们被内部上拉为高电平 并用作输入 作为输入 由于外部下拉 为低电平 P3 口将输出电流 ILL 这是由于上拉的缘故 中文科技文献 6 P3 口也可作为 AT89C51 的一些特殊功能口 如下表所示 口管脚 备选功能 P3 0 RXD 串行输入口 P3 1 TXD 串行输出口 P3 2 INT0 外部中断 0 P3 3 INT1 外部中断 1 P3 4 T0 记时器 0 外部输入 P3 5 T1 记时器 1 外部输入 P3 6 WR 外部数据存储器写选通 P3 7 RD 外部数据存储器读选通 P3 口同时为闪烁编程和编程校验接收一些控制信号 RST 复位输入 当振荡器复位器件时 要保持 RST 脚两个机器周期的高电平时间 ALE PROG 当访问外部存储器时 地址锁存允许的输出电平用于锁存地址的地位字节 在 FLASH 编程期间 此引脚用于输入编程脉冲 在平时 ALE 端以不变的频率周期输